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Use consistent types for holding instructions, instruction masks, etc.

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include/
	* opcode/ppc.h (PPC_INT_FMT): Define.
	(struct powerpc_opcode) <opcode>: Update type.
	(struct powerpc_opcode) <mask>: Likewise.
	(struct powerpc_opcode) <bitm>: Likewise.
	(struct powerpc_opcode) <insert>: Likewise.
	(struct powerpc_opcode) <extract>: Likewise.
	(ppc_optional_operand_value): Likewise.

gas/
	* config/tc-ppc.c (last_insn): Update type.
	(insn_validate) <omask, mask>: Likewise.
	(ppc_setup_opcodes) <mask, right_bit>: Likewise.
	<PRINT_OPCODE_TABLE>: Update types and printf format specifiers.
	(ppc_insert_operand): Update return and argument types and remove
	unneeded type casts.
	<min, max, right, tmp>: Update type.
	(md_assemble): Remove unneeded type casts.
	<insn, val, tmp_insn>: Update type.

opcodes/
	* opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
	(operand_value_powerpc): Update return and argument type.
	<value, top>: Update type.
	(skip_optional_operands): Update argument type.
	(lookup_powerpc): Likewise.
	(lookup_vle): Likewise.
	<table_opcd, table_mask, insn2>: Update type.
	(lookup_spe2): Update argument type.
	<table_opcd, table_mask, insn2>: Update type.
	(print_insn_powerpc) <insn, value>: Update type.
	Use PPC_INT_FMT for printing instructions and operands.
	* opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
	insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
	insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
	extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
	extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
	insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
	extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
	insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
	extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
	insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
	extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
	insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
	extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
	insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
	extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
	insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
	extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
	insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
	extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
	extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
	extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
	insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
	extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
	insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
	extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
	extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
	(OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
	BD24, BBO, Y_MASK  , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
	DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
	SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
	VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
	VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
	VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
	XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
	XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
	XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
	XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
This commit is contained in:
Peter Bergner 2017-12-01 11:20:15 -06:00
parent d0df06af9b
commit 0f873fd58b
7 changed files with 625 additions and 556 deletions
Download patch file Download diff file Expand all files Collapse all files

12
gas/ChangeLog
View file

@ -1,3 +1,15 @@
2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
* config/tc-ppc.c (last_insn): Update type.
(insn_validate) <omask, mask>: Likewise.
(ppc_setup_opcodes) <mask, right_bit>: Likewise.
<PRINT_OPCODE_TABLE>: Update types and printf format specifiers.
(ppc_insert_operand): Update return and argument types and remove
unneeded type casts.
<min, max, right, tmp>: Update type.
(md_assemble): Remove unneeded type casts.
<insn, val, tmp_insn>: Update type.
2017-11-29 Jan Beulich <jbeulich@suse.com> 2017-11-29 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (enum i386_error): Remove try_vector_disp8. * config/tc-i386.c (enum i386_error): Remove try_vector_disp8.

64
gas/config/tc-ppc.c
View file

@ -217,7 +217,7 @@ static enum {
/* Warn on emitting data to code sections. */ /* Warn on emitting data to code sections. */
int warn_476; int warn_476;
unsigned long last_insn; uint64_t last_insn;
segT last_seg; segT last_seg;
subsegT last_subseg; subsegT last_subseg;
@ -1497,7 +1497,7 @@ static bfd_boolean
insn_validate (const struct powerpc_opcode *op) insn_validate (const struct powerpc_opcode *op)
{ {
const unsigned char *o; const unsigned char *o;
unsigned long omask = op->mask; uint64_t omask = op->mask;
/* The mask had better not trim off opcode bits. */ /* The mask had better not trim off opcode bits. */
if ((op->opcode & omask) != op->opcode) if ((op->opcode & omask) != op->opcode)
@ -1519,7 +1519,7 @@ insn_validate (const struct powerpc_opcode *op)
const struct powerpc_operand *operand = &powerpc_operands[*o]; const struct powerpc_operand *operand = &powerpc_operands[*o];
if (operand->shift != (int) PPC_OPSHIFT_INV) if (operand->shift != (int) PPC_OPSHIFT_INV)
{ {
unsigned long mask; uint64_t mask;
if (operand->shift >= 0) if (operand->shift >= 0)
mask = operand->bitm << operand->shift; mask = operand->bitm << operand->shift;
@ -1570,8 +1570,8 @@ ppc_setup_opcodes (void)
all the 1's in the mask are contiguous. */ all the 1's in the mask are contiguous. */
for (i = 0; i < num_powerpc_operands; ++i) for (i = 0; i < num_powerpc_operands; ++i)
{ {
unsigned long mask = powerpc_operands[i].bitm; uint64_t mask = powerpc_operands[i].bitm;
unsigned long right_bit; uint64_t right_bit;
unsigned int j; unsigned int j;
right_bit = mask & -mask; right_bit = mask & -mask;
@ -1604,10 +1604,10 @@ ppc_setup_opcodes (void)
int new_opcode = PPC_OP (op[0].opcode); int new_opcode = PPC_OP (op[0].opcode);
#ifdef PRINT_OPCODE_TABLE #ifdef PRINT_OPCODE_TABLE
printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n", printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
op->name, (unsigned int) (op - powerpc_opcodes), op->name, (unsigned int) (op - powerpc_opcodes),
(unsigned int) new_opcode, (unsigned int) op->opcode, (unsigned int) new_opcode, (unsigned long long) op->opcode,
(unsigned int) op->mask, (unsigned long long) op->flags); (unsigned long long) op->mask, (unsigned long long) op->flags);
#endif #endif
/* The major opcodes had better be sorted. Code in the /* The major opcodes had better be sorted. Code in the
@ -1669,10 +1669,10 @@ ppc_setup_opcodes (void)
new_seg = VLE_OP_TO_SEG (new_seg); new_seg = VLE_OP_TO_SEG (new_seg);
#ifdef PRINT_OPCODE_TABLE #ifdef PRINT_OPCODE_TABLE
printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n", printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
op->name, (unsigned int) (op - powerpc_opcodes), op->name, (unsigned int) (op - powerpc_opcodes),
(unsigned int) new_seg, (unsigned int) op->opcode, (unsigned int) new_seg, (unsigned long long) op->opcode,
(unsigned int) op->mask, (unsigned long long) op->flags); (unsigned long long) op->mask, (unsigned long long) op->flags);
#endif #endif
/* The major opcodes had better be sorted. Code in the /* The major opcodes had better be sorted. Code in the
disassembler assumes the insns are sorted according to disassembler assumes the insns are sorted according to
@ -1884,15 +1884,15 @@ ppc_cleanup (void)
/* Insert an operand value into an instruction. */ /* Insert an operand value into an instruction. */
static unsigned long static uint64_t
ppc_insert_operand (unsigned long insn, ppc_insert_operand (uint64_t insn,
const struct powerpc_operand *operand, const struct powerpc_operand *operand,
offsetT val, int64_t val,
ppc_cpu_t cpu, ppc_cpu_t cpu,
const char *file, const char *file,
unsigned int line) unsigned int line)
{ {
long min, max, right; int64_t min, max, right;
max = operand->bitm; max = operand->bitm;
right = max & -max; right = max & -max;
@ -1921,7 +1921,7 @@ ppc_insert_operand (unsigned long insn,
if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
{ {
long tmp = min; int64_t tmp = min;
min = -max; min = -max;
max = -tmp; max = -tmp;
} }
@ -1934,18 +1934,18 @@ ppc_insert_operand (unsigned long insn,
sign extend the 32-bit value to 64 bits if so doing makes the sign extend the 32-bit value to 64 bits if so doing makes the
value valid. */ value valid. */
if (val > max if (val > max
&& (offsetT) (val - 0x80000000 - 0x80000000) >= min && (val - (1LL << 32)) >= min
&& (offsetT) (val - 0x80000000 - 0x80000000) <= max && (val - (1LL << 32)) <= max
&& ((val - 0x80000000 - 0x80000000) & (right - 1)) == 0) && ((val - (1LL << 32)) & (right - 1)) == 0)
val = val - 0x80000000 - 0x80000000; val = val - (1LL << 32);
/* Similarly, people write expressions like ~(1<<15), and expect /* Similarly, people write expressions like ~(1<<15), and expect
this to be OK for a 32-bit unsigned value. */ this to be OK for a 32-bit unsigned value. */
else if (val < min else if (val < min
&& (offsetT) (val + 0x80000000 + 0x80000000) >= min && (val + (1LL << 32)) >= min
&& (offsetT) (val + 0x80000000 + 0x80000000) <= max && (val + (1LL << 32)) <= max
&& ((val + 0x80000000 + 0x80000000) & (right - 1)) == 0) && ((val + (1LL << 32)) & (right - 1)) == 0)
val = val + 0x80000000 + 0x80000000; val = val + (1LL << 32);
else if (val < min else if (val < min
|| val > max || val > max
@ -1958,14 +1958,14 @@ ppc_insert_operand (unsigned long insn,
const char *errmsg; const char *errmsg;
errmsg = NULL; errmsg = NULL;
insn = (*operand->insert) (insn, (long) val, cpu, &errmsg); insn = (*operand->insert) (insn, val, cpu, &errmsg);
if (errmsg != (const char *) NULL) if (errmsg != (const char *) NULL)
as_bad_where (file, line, "%s", errmsg); as_bad_where (file, line, "%s", errmsg);
} }
else if (operand->shift >= 0) else if (operand->shift >= 0)
insn |= ((long) val & operand->bitm) << operand->shift; insn |= (val & operand->bitm) << operand->shift;
else else
insn |= ((long) val & operand->bitm) >> -operand->shift; insn |= (val & operand->bitm) >> -operand->shift;
return insn; return insn;
} }
@ -2739,7 +2739,7 @@ md_assemble (char *str)
{ {
char *s; char *s;
const struct powerpc_opcode *opcode; const struct powerpc_opcode *opcode;
unsigned long insn; uint64_t insn;
const unsigned char *opindex_ptr; const unsigned char *opindex_ptr;
int skip_optional; int skip_optional;
int need_paren; int need_paren;
@ -2868,7 +2868,7 @@ md_assemble (char *str)
&& !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64) && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)
&& skip_optional) && skip_optional)
{ {
long val = ppc_optional_operand_value (operand); int64_t val = ppc_optional_operand_value (operand);
if (operand->insert) if (operand->insert)
{ {
insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg); insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg);
@ -2876,9 +2876,9 @@ md_assemble (char *str)
as_bad ("%s", errmsg); as_bad ("%s", errmsg);
} }
else if (operand->shift >= 0) else if (operand->shift >= 0)
insn |= ((long) val & operand->bitm) << operand->shift; insn |= (val & operand->bitm) << operand->shift;
else else
insn |= ((long) val & operand->bitm) >> -operand->shift; insn |= (val & operand->bitm) >> -operand->shift;
if ((operand->flags & PPC_OPERAND_NEXT) != 0) if ((operand->flags & PPC_OPERAND_NEXT) != 0)
next_opindex = *opindex_ptr + 1; next_opindex = *opindex_ptr + 1;
@ -3219,7 +3219,7 @@ md_assemble (char *str)
/* If VLE-mode convert LO/HI/HA relocations. */ /* If VLE-mode convert LO/HI/HA relocations. */
if (opcode->flags & PPC_OPCODE_VLE) if (opcode->flags & PPC_OPCODE_VLE)
{ {
int tmp_insn = insn & opcode->mask; uint64_t tmp_insn = insn & opcode->mask;
int use_a_reloc = (tmp_insn == E_OR2I_INSN int use_a_reloc = (tmp_insn == E_OR2I_INSN
|| tmp_insn == E_AND2I_DOT_INSN || tmp_insn == E_AND2I_DOT_INSN

10
include/ChangeLog
View file

@ -1,3 +1,13 @@
2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
* opcode/ppc.h (PPC_INT_FMT): Define.
(struct powerpc_opcode) <opcode>: Update type.
(struct powerpc_opcode) <mask>: Likewise.
(struct powerpc_opcode) <bitm>: Likewise.
(struct powerpc_opcode) <insert>: Likewise.
(struct powerpc_opcode) <extract>: Likewise.
(ppc_optional_operand_value): Likewise.
2017-11-24 H.J. Lu <hongjiu.lu@intel.com> 2017-11-24 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/22444 PR binutils/22444

22
include/opcode/ppc.h
View file

@ -30,6 +30,14 @@ extern "C" {
typedef uint64_t ppc_cpu_t; typedef uint64_t ppc_cpu_t;
#if BFD_HOST_64BIT_LONG
# define PPC_INT_FMT "l"
#elif defined (__MSVCRT__)
# define PPC_INT_FMT "I64"
#else
# define PPC_INT_FMT "ll"
#endif
/* The opcode table is an array of struct powerpc_opcode. */ /* The opcode table is an array of struct powerpc_opcode. */
struct powerpc_opcode struct powerpc_opcode
@ -39,13 +47,13 @@ struct powerpc_opcode
/* The opcode itself. Those bits which will be filled in with /* The opcode itself. Those bits which will be filled in with
operands are zeroes. */ operands are zeroes. */
unsigned long opcode; uint64_t opcode;
/* The opcode mask. This is used by the disassembler. This is a /* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */ match (and are presumably filled in by operands). */
unsigned long mask; uint64_t mask;
/* One bit flags for the opcode. These are used to indicate which /* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The defined values specific processors support the instructions. The defined values
@ -249,7 +257,7 @@ extern const int spe2_num_opcodes;
struct powerpc_operand struct powerpc_operand
{ {
/* A bitmask of bits in the operand. */ /* A bitmask of bits in the operand. */
unsigned int bitm; uint64_t bitm;
/* The shift operation to be applied to the operand. No shift /* The shift operation to be applied to the operand. No shift
is made if this is zero. For positive values, the operand is made if this is zero. For positive values, the operand
@ -277,8 +285,8 @@ struct powerpc_operand
string (the operand will be inserted in any case). If the string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged (most operands operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */ can accept any value). */
unsigned long (*insert) uint64_t (*insert)
(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg);
/* Extraction function. This is used by the disassembler. To /* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field. extract this operand type from an instruction, check this field.
@ -299,7 +307,7 @@ struct powerpc_operand
non-zero if this operand type can not actually be extracted from non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */ operand is valid, *INVALID will not be changed. */
long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid);
/* One bit syntax flags. */ /* One bit syntax flags. */
unsigned long flags; unsigned long flags;
@ -463,7 +471,7 @@ extern const int powerpc_num_macros;
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
static inline long static inline int64_t
ppc_optional_operand_value (const struct powerpc_operand *operand) ppc_optional_operand_value (const struct powerpc_operand *operand)
{ {
if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0) if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)

51
opcodes/ChangeLog
View file

@ -1,3 +1,54 @@
2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
* opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
(operand_value_powerpc): Update return and argument type.
<value, top>: Update type.
(skip_optional_operands): Update argument type.
(lookup_powerpc): Likewise.
(lookup_vle): Likewise.
<table_opcd, table_mask, insn2>: Update type.
(lookup_spe2): Update argument type.
<table_opcd, table_mask, insn2>: Update type.
(print_insn_powerpc) <insn, value>: Update type.
Use PPC_INT_FMT for printing instructions and operands.
* opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
(OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
2017-11-29 Jan Beulich <jbeulich@suse.com> 2017-11-29 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (active_cpu_flags, active_isstring, enum stage): * i386-gen.c (active_cpu_flags, active_isstring, enum stage):

90
opcodes/ppc-dis.c
View file

@ -381,39 +381,36 @@ disassemble_init_powerpc (struct disassemble_info *info)
if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0) if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
{ {
i = powerpc_num_opcodes; i = powerpc_num_opcodes;
while (--i >= 0) while (--i >= 0)
{ {
unsigned op = PPC_OP (powerpc_opcodes[i].opcode); unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
powerpc_opcd_indices[op] = i;
powerpc_opcd_indices[op] = i; }
}
last = powerpc_num_opcodes; last = powerpc_num_opcodes;
for (i = PPC_OPCD_SEGS; i > 0; --i) for (i = PPC_OPCD_SEGS; i > 0; --i)
{ {
if (powerpc_opcd_indices[i] == 0) if (powerpc_opcd_indices[i] == 0)
powerpc_opcd_indices[i] = last; powerpc_opcd_indices[i] = last;
last = powerpc_opcd_indices[i]; last = powerpc_opcd_indices[i];
} }
i = vle_num_opcodes; i = vle_num_opcodes;
while (--i >= 0) while (--i >= 0)
{ {
unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask); unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
unsigned seg = VLE_OP_TO_SEG (op); unsigned seg = VLE_OP_TO_SEG (op);
vle_opcd_indices[seg] = i;
vle_opcd_indices[seg] = i; }
}
last = vle_num_opcodes; last = vle_num_opcodes;
for (i = VLE_OPCD_SEGS; i > 0; --i) for (i = VLE_OPCD_SEGS; i > 0; --i)
{ {
if (vle_opcd_indices[i] == 0) if (vle_opcd_indices[i] == 0)
vle_opcd_indices[i] = last; vle_opcd_indices[i] = last;
last = vle_opcd_indices[i]; last = vle_opcd_indices[i];
} }
} }
/* SPE2 opcodes */ /* SPE2 opcodes */
@ -422,7 +419,6 @@ disassemble_init_powerpc (struct disassemble_info *info)
{ {
unsigned xop = SPE2_XOP (spe2_opcodes[i].opcode); unsigned xop = SPE2_XOP (spe2_opcodes[i].opcode);
unsigned seg = SPE2_XOP_TO_SEG (xop); unsigned seg = SPE2_XOP_TO_SEG (xop);
spe2_opcd_indices[seg] = i; spe2_opcd_indices[seg] = i;
} }
@ -464,11 +460,11 @@ print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
/* Extract the operand value from the PowerPC or POWER instruction. */ /* Extract the operand value from the PowerPC or POWER instruction. */
static long static int64_t
operand_value_powerpc (const struct powerpc_operand *operand, operand_value_powerpc (const struct powerpc_operand *operand,
unsigned long insn, ppc_cpu_t dialect) uint64_t insn, ppc_cpu_t dialect)
{ {
long value; int64_t value;
int invalid; int invalid;
/* Extract the value from the instruction. */ /* Extract the value from the instruction. */
if (operand->extract) if (operand->extract)
@ -483,7 +479,7 @@ operand_value_powerpc (const struct powerpc_operand *operand,
{ {
/* BITM is always some number of zeros followed by some /* BITM is always some number of zeros followed by some
number of ones, followed by some number of zeros. */ number of ones, followed by some number of zeros. */
unsigned long top = operand->bitm; uint64_t top = operand->bitm;
/* top & -top gives the rightmost 1 bit, so this /* top & -top gives the rightmost 1 bit, so this
fills in any trailing zeros. */ fills in any trailing zeros. */
top |= (top & -top) - 1; top |= (top & -top) - 1;
@ -499,7 +495,7 @@ operand_value_powerpc (const struct powerpc_operand *operand,
static int static int
skip_optional_operands (const unsigned char *opindex, skip_optional_operands (const unsigned char *opindex,
unsigned long insn, ppc_cpu_t dialect) uint64_t insn, ppc_cpu_t dialect)
{ {
const struct powerpc_operand *operand; const struct powerpc_operand *operand;
@ -519,7 +515,7 @@ skip_optional_operands (const unsigned char *opindex,
/* Find a match for INSN in the opcode table, given machine DIALECT. */ /* Find a match for INSN in the opcode table, given machine DIALECT. */
static const struct powerpc_opcode * static const struct powerpc_opcode *
lookup_powerpc (unsigned long insn, ppc_cpu_t dialect) lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
{ {
const struct powerpc_opcode *opcode, *opcode_end, *last; const struct powerpc_opcode *opcode, *opcode_end, *last;
unsigned long op; unsigned long op;
@ -570,7 +566,7 @@ lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
/* Find a match for INSN in the VLE opcode table. */ /* Find a match for INSN in the VLE opcode table. */
static const struct powerpc_opcode * static const struct powerpc_opcode *
lookup_vle (unsigned long insn) lookup_vle (uint64_t insn)
{ {
const struct powerpc_opcode *opcode; const struct powerpc_opcode *opcode;
const struct powerpc_opcode *opcode_end; const struct powerpc_opcode *opcode_end;
@ -590,10 +586,10 @@ lookup_vle (unsigned long insn)
opcode < opcode_end; opcode < opcode_end;
++opcode) ++opcode)
{ {
unsigned long table_opcd = opcode->opcode; uint64_t table_opcd = opcode->opcode;
unsigned long table_mask = opcode->mask; uint64_t table_mask = opcode->mask;
bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask); bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
unsigned long insn2; uint64_t insn2;
const unsigned char *opindex; const unsigned char *opindex;
const struct powerpc_operand *operand; const struct powerpc_operand *operand;
int invalid; int invalid;
@ -624,7 +620,7 @@ lookup_vle (unsigned long insn)
/* Find a match for INSN in the SPE2 opcode table. */ /* Find a match for INSN in the SPE2 opcode table. */
static const struct powerpc_opcode * static const struct powerpc_opcode *
lookup_spe2 (unsigned long insn) lookup_spe2 (uint64_t insn)
{ {
const struct powerpc_opcode *opcode, *opcode_end; const struct powerpc_opcode *opcode, *opcode_end;
unsigned op, xop, seg; unsigned op, xop, seg;
@ -645,9 +641,9 @@ lookup_spe2 (unsigned long insn)
opcode < opcode_end; opcode < opcode_end;
++opcode) ++opcode)
{ {
unsigned long table_opcd = opcode->opcode; uint64_t table_opcd = opcode->opcode;
unsigned long table_mask = opcode->mask; uint64_t table_mask = opcode->mask;
unsigned long insn2; uint64_t insn2;
const unsigned char *opindex; const unsigned char *opindex;
const struct powerpc_operand *operand; const struct powerpc_operand *operand;
int invalid; int invalid;
@ -683,7 +679,7 @@ print_insn_powerpc (bfd_vma memaddr,
{ {
bfd_byte buffer[4]; bfd_byte buffer[4];
int status; int status;
unsigned long insn; uint64_t insn;
const struct powerpc_opcode *opcode; const struct powerpc_opcode *opcode;
bfd_boolean insn_is_short; bfd_boolean insn_is_short;
@ -753,7 +749,7 @@ print_insn_powerpc (bfd_vma memaddr,
skip_optional = -1; skip_optional = -1;
for (opindex = opcode->operands; *opindex != 0; opindex++) for (opindex = opcode->operands; *opindex != 0; opindex++)
{ {
long value; int64_t value;
operand = powerpc_operands + *opindex; operand = powerpc_operands + *opindex;
@ -785,27 +781,27 @@ print_insn_powerpc (bfd_vma memaddr,
/* Print the operand as directed by the flags. */ /* Print the operand as directed by the flags. */
if ((operand->flags & PPC_OPERAND_GPR) != 0 if ((operand->flags & PPC_OPERAND_GPR) != 0
|| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
(*info->fprintf_func) (info->stream, "r%ld", value); (*info->fprintf_func) (info->stream, "r%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_FPR) != 0) else if ((operand->flags & PPC_OPERAND_FPR) != 0)
(*info->fprintf_func) (info->stream, "f%ld", value); (*info->fprintf_func) (info->stream, "f%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_VR) != 0) else if ((operand->flags & PPC_OPERAND_VR) != 0)
(*info->fprintf_func) (info->stream, "v%ld", value); (*info->fprintf_func) (info->stream, "v%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_VSR) != 0) else if ((operand->flags & PPC_OPERAND_VSR) != 0)
(*info->fprintf_func) (info->stream, "vs%ld", value); (*info->fprintf_func) (info->stream, "vs%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
(*info->print_address_func) (memaddr + value, info); (*info->print_address_func) (memaddr + value, info);
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
else if ((operand->flags & PPC_OPERAND_FSL) != 0) else if ((operand->flags & PPC_OPERAND_FSL) != 0)
(*info->fprintf_func) (info->stream, "fsl%ld", value); (*info->fprintf_func) (info->stream, "fsl%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_FCR) != 0) else if ((operand->flags & PPC_OPERAND_FCR) != 0)
(*info->fprintf_func) (info->stream, "fcr%ld", value); (*info->fprintf_func) (info->stream, "fcr%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_UDI) != 0) else if ((operand->flags & PPC_OPERAND_UDI) != 0)
(*info->fprintf_func) (info->stream, "%ld", value); (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
&& (((dialect & PPC_OPCODE_PPC) != 0) && (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0))) || ((dialect & PPC_OPCODE_VLE) != 0)))
(*info->fprintf_func) (info->stream, "cr%ld", value); (*info->fprintf_func) (info->stream, "cr%" PPC_INT_FMT "d", value);
else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0) else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
&& (((dialect & PPC_OPCODE_PPC) != 0) && (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0))) || ((dialect & PPC_OPCODE_VLE) != 0)))
@ -821,7 +817,7 @@ print_insn_powerpc (bfd_vma memaddr,
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]); (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
} }
else else
(*info->fprintf_func) (info->stream, "%d", (int) value); (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
if (need_paren) if (need_paren)
{ {
@ -851,7 +847,7 @@ print_insn_powerpc (bfd_vma memaddr,
} }
/* We could not find a match. */ /* We could not find a match. */
(*info->fprintf_func) (info->stream, ".long 0x%lx", insn); (*info->fprintf_func) (info->stream, ".long 0x%" PPC_INT_FMT "x", insn);
return 4; return 4;
} }

932
opcodes/ppc-opc.c
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