gas/testsuite/
* gas/ppc/e500mc.d ("lfdepx", "stfdepx"): Fix tests to expect a floating point register. opcodes/ * ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first operand to be a float point register (FRT/FRS).
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4 changed files with 14 additions and 4 deletions
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@ -1,3 +1,8 @@
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2009-02-19 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first
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operand to be a float point register (FRT/FRS).
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2009-02-18 Adam Nemet <anemet@caviumnetworks.com>
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* mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific
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@ -4286,7 +4286,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}},
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{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
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{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
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{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, PPCNONE, {FRT, RB}},
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{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
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@ -4373,7 +4373,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
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{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
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{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
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{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
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{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, PPCNONE, {RT, FRB}},
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{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
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