FreeChainXenon/binutils-gdb
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

* simops.c: Fix carry bit computation for "add" instructions.

Browse source 
More bugs exposed by new mn10300 compiler optimizations.
This commit is contained in:
Jeff Law 1997-03-12 22:20:13 +00:00
parent 09eef8af93
commit 0ade484f98
2 changed files with 13 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
sim/mn10300/ChangeLog
View file

@ -1,5 +1,7 @@
Wed Mar 12 15:04:00 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix carry bit computation for "add" instructions.
* simops.c: Fix typos in bset insns. Fix arguments to store_mem
for bset imm8,(d8,an) and bclr imm8,(d8,an).

22
sim/mn10300/simops.c
View file

@ -997,7 +997,7 @@ void OP_E0 (insn, extension)
z = (value == 0);
n = (value & 0x80000000);
c = (reg1 < reg2);
c = (value < reg1) || (value < reg2);
v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
&& (reg2 & 0x80000000) != (value & 0x80000000));
@ -1020,7 +1020,7 @@ void OP_F160 (insn, extension)
z = (value == 0);
n = (value & 0x80000000);
c = (reg1 < reg2);
c = (value < reg1) || (value < reg2);
v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
&& (reg2 & 0x80000000) != (value & 0x80000000));
@ -1043,7 +1043,7 @@ void OP_F150 (insn, extension)
z = (value == 0);
n = (value & 0x80000000);
c = (reg1 < reg2);
c = (value < reg1) || (value < reg2);
v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
&& (reg2 & 0x80000000) != (value & 0x80000000));
@ -1066,7 +1066,7 @@ void OP_F170 (insn, extension)
z = (value == 0);
n = (value & 0x80000000);
c = (reg1 < reg2);
c = (value < reg1) || (value < reg2);
v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
&& (reg2 & 0x80000000) != (value & 0x80000000));
@ -1089,7 +1089,7 @@ void OP_2800 (insn, extension)
z = (value == 0);
n = (value & 0x80000000);
c = (reg1 < imm);
c = (value < reg1) || (value < imm);
v = ((reg1 & 0x80000000) == (imm & 0x80000000)
&& (reg1 & 0x80000000) != (value & 0x80000000));
@ -1112,7 +1112,7 @@ void OP_FAC00000 (insn, extension)
z = (value == 0);
n = (value & 0x80000000);
c = (reg1 < imm);
c = (value < reg1) || (value < imm);
v = ((reg1 & 0x80000000) == (imm & 0x80000000)
&& (reg1 & 0x80000000) != (value & 0x80000000));
@ -1135,7 +1135,7 @@ void OP_FCC00000 (insn, extension)
z = (value == 0);
n = (value & 0x80000000);
c = (reg1 < imm);
c = (value < reg1) || (value < imm);
v = ((reg1 & 0x80000000) == (imm & 0x80000000)
&& (reg1 & 0x80000000) != (value & 0x80000000));
@ -1158,7 +1158,7 @@ void OP_2000 (insn, extension)
z = (value == 0);
n = (value & 0x80000000);
c = (reg1 < imm);
c = (value < reg1) || (value < imm);
v = ((reg1 & 0x80000000) == (imm & 0x80000000)
&& (reg1 & 0x80000000) != (value & 0x80000000));
@ -1181,7 +1181,7 @@ void OP_FAD00000 (insn, extension)
z = (value == 0);
n = (value & 0x80000000);
c = (reg1 < imm);
c = (value < reg1) || (value < imm);
v = ((reg1 & 0x80000000) == (imm & 0x80000000)
&& (reg1 & 0x80000000) != (value & 0x80000000));
@ -1204,7 +1204,7 @@ void OP_FCD00000 (insn, extension)
z = (value == 0);
n = (value & 0x80000000);
c = (reg1 < imm);
c = (value < reg1) || (value < imm);
v = ((reg1 & 0x80000000) == (imm & 0x80000000)
&& (reg1 & 0x80000000) != (value & 0x80000000));
@ -1263,7 +1263,7 @@ void OP_F140 (insn, extension)
z = (value == 0);
n = (value & 0x80000000);
c = (reg1 < reg2);
c = (value < reg1) || (value < reg2);
v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
&& (reg2 & 0x80000000) != (value & 0x80000000));