Handle indirect branches for AMD64 and Intel64
AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode.
AMD64 supports indirect branches with 16-bit address via the data size
prefix while the data size prefix is ignored by Intel64.
gas/
PR binutis/18386
* testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
* testsuite/gas/i386/x86-64-branch.d: Updated.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
* testsuite/gas/i386/x86-64-branch-4.l: New file.
* testsuite/gas/i386/x86-64-branch-4.s: Likewise.
opcodes/
PR binutis/18386
* i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
(indir_v_mode): New.
Add comments for '&'.
(reg_table): Replace "{T|}" with "{&|}" on call and jmp.
(putop): Handle '&'.
(intel_operand_size): Handle indir_v_mode.
(OP_E_register): Likewise.
* i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
64-bit indirect call/jmp for AMD64.
* i386-tbl.h: Regenerated
This commit is contained in:
H.J. Lu
parent
1aa70332ca
commit
07f5af7d3c
10 changed files with 158 additions and 31 deletions
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@ -1,3 +1,12 @@
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2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
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PR binutis/18386
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* testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
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* testsuite/gas/i386/x86-64-branch.d: Updated.
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* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
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* testsuite/gas/i386/x86-64-branch-4.l: New file.
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* testsuite/gas/i386/x86-64-branch-4.s: Likewise.
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2016-06-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/tc-aarch64.c (aarch64_cpus): Add cortex-a73 entry.
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@ -816,6 +816,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-jump"
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run_dump_test "x86-64-branch-2"
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run_list_test "x86-64-branch-3" "-al -mintel64"
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run_list_test "x86-64-branch-4" "-al -mintel64"
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run_dump_test "x86-64-gotpcrel"
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run_dump_test "x86-64-gotpcrel-no-relax"
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@ -10,14 +10,14 @@ Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
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[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
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[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\)
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[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff 10 data16 callq \*\(%rax\)
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[ ]*[a-f0-9]+: ff e0 jmpq \*%rax
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[ ]*[a-f0-9]+: ff e0 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
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[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff 20 data16 jmpq \*\(%rax\)
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[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x1f 1b: R_X86_64_PC32 \*ABS\*\+0x10003c
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[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x24 20: R_X86_64_PC32 \*ABS\*\+0x10003c
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[ ]*[a-f0-9]+: 66 e8 00 00 00 00 data16 callq 0x2a 26: R_X86_64_PC32 foo-0x4
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@ -25,14 +25,14 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 82 00 00 00 00 data16 jb 0x37 33: R_X86_64_PC32 foo-0x4
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
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[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
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[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\)
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[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff 10 data16 callq \*\(%rax\)
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[ ]*[a-f0-9]+: ff e0 jmpq \*%rax
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[ ]*[a-f0-9]+: ff e0 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
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[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff 20 data16 jmpq \*\(%rax\)
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[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x56 52: R_X86_64_PC32 \*ABS\*\+0x10003c
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[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x5b 57: R_X86_64_PC32 \*ABS\*\+0x10003c
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#pass
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33
gas/testsuite/gas/i386/x86-64-branch-4.l
Normal file
33
gas/testsuite/gas/i386/x86-64-branch-4.l
Normal file
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@ -0,0 +1,33 @@
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.*: Assembler messages:
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.*:2: Error: invalid instruction suffix for `call'
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.*:3: Error: invalid instruction suffix for `call'
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.*:4: Error: operand type mismatch for `jmp'
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.*:5: Error: invalid instruction suffix for `jmp'
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.*:6: Error: invalid instruction suffix for `jmp'
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.*:9: Error: operand type mismatch for `call'
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.*:10: Error: invalid instruction suffix for `call'
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.*:11: Error: invalid instruction suffix for `call'
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.*:12: Error: invalid instruction suffix for `call'
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.*:13: Error: operand type mismatch for `jmp'
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.*:14: Error: invalid instruction suffix for `jmp'
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.*:15: Error: invalid instruction suffix for `jmp'
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.*:16: Error: invalid instruction suffix for `jmp'
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GAS LISTING .*
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#...
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[ ]*1[ ]+\.text
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[ ]*2[ ]+callw \*%ax
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[ ]*3[ ]+callw \*\(%rax\)
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[ ]*4[ ]+jmp \*%ax
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[ ]*5[ ]+jmpw \*%ax
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[ ]*6[ ]+jmpw \*\(%rax\)
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[ ]*7[ ]+
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[ ]*8[ ]+\.intel_syntax noprefix
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[ ]*9[ ]+call ax
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[ ]*10[ ]+callw ax
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[ ]*11[ ]+callw \[rax\]
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[ ]*12[ ]+call WORD PTR \[rax\]
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[ ]*13[ ]+jmp ax
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[ ]*14[ ]+jmpw ax
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[ ]*15[ ]+jmpw \[rax\]
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[ ]*16[ ]+jmp WORD PTR \[rax\]
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#pass
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16
gas/testsuite/gas/i386/x86-64-branch-4.s
Normal file
16
gas/testsuite/gas/i386/x86-64-branch-4.s
Normal file
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@ -0,0 +1,16 @@
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.text
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callw *%ax
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callw *(%rax)
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jmp *%ax
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jmpw *%ax
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jmpw *(%rax)
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.intel_syntax noprefix
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call ax
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callw ax
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callw [rax]
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call WORD PTR [rax]
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jmp ax
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jmpw ax
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jmpw [rax]
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jmp WORD PTR [rax]
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@ -9,14 +9,14 @@ Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
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[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
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[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\)
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[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff 10 data16 callq \*\(%rax\)
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[ ]*[a-f0-9]+: ff e0 jmpq \*%rax
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[ ]*[a-f0-9]+: ff e0 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
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[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff 20 data16 jmpq \*\(%rax\)
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[ ]*[a-f0-9]+: e8 (00|5b) 00 (00|10) 00 callq (0x1f|10007a <.text\+0x10007a>)
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[ ]*[a-f0-9]+: e9 (00|60) 00 (00|10) 00 jmpq (0x24|100084 <.text\+0x100084>)
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[ ]*[a-f0-9]+: 66 e8 00 00 00 00 data16 callq (0x2a|2a <.text\+0x2a>)
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@ -24,14 +24,14 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 82 00 00 00 00 data16 jb (0x37|37 <.text\+0x37>)
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: ff d0 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
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[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax
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[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\)
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[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
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[ ]*[a-f0-9]+: 66 ff 10 data16 callq \*\(%rax\)
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[ ]*[a-f0-9]+: ff e0 jmpq \*%rax
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[ ]*[a-f0-9]+: ff e0 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax
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[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\)
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[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
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[ ]*[a-f0-9]+: 66 ff 20 data16 jmpq \*\(%rax\)
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[ ]*[a-f0-9]+: e8 (00|92) 00 (00|10) 00 callq (0x56|1000e8 <.text\+0x1000e8>)
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[ ]*[a-f0-9]+: e9 (00|97) 00 (00|10) 00 jmpq (0x5b|1000f2 <.text\+0x1000f2>)
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#pass
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@ -1,3 +1,17 @@
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2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
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PR binutis/18386
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* i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
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(indir_v_mode): New.
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Add comments for '&'.
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(reg_table): Replace "{T|}" with "{&|}" on call and jmp.
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(putop): Handle '&'.
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(intel_operand_size): Handle indir_v_mode.
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(OP_E_register): Likewise.
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* i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
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64-bit indirect call/jmp for AMD64.
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* i386-tbl.h: Regenerated
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2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-dis.c (struct arc_operand_iterator): New structure.
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@ -258,7 +258,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define Edw { OP_E, dw_mode }
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#define Edqd { OP_E, dqd_mode }
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#define Eq { OP_E, q_mode }
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#define indirEv { OP_indirE, stack_v_mode }
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#define indirEv { OP_indirE, indir_v_mode }
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#define indirEp { OP_indirE, f_mode }
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#define stackEv { OP_E, stack_v_mode }
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#define Em { OP_E, m_mode }
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@ -561,6 +561,8 @@ enum
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/* 4- or 6-byte pointer operand */
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f_mode,
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const_1_mode,
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/* v_mode for indirect branch opcodes. */
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indir_v_mode,
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/* v_mode for stack-related opcodes. */
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stack_v_mode,
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/* non-quad operand size depends on prefixes */
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@ -2483,6 +2485,9 @@ struct dis386 {
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suffix_always is true (lcall/ljmp).
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'@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
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on operand size prefix.
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'&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
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has no operand size prefix for AMD64 ISA, behave as 'P'
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otherwise
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2 upper case letter macros:
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"XY" => print 'x' or 'y' if suffix_always is true or no register
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@ -3531,9 +3536,9 @@ static const struct dis386 reg_table[][8] = {
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{
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{ "incQ", { Evh1 }, 0 },
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{ "decQ", { Evh1 }, 0 },
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{ "call{T|}", { indirEv, BND }, 0 },
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{ "call{&|}", { indirEv, BND }, 0 },
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{ MOD_TABLE (MOD_FF_REG_3) },
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{ "jmp{T|}", { indirEv, BND }, 0 },
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{ "jmp{&|}", { indirEv, BND }, 0 },
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{ MOD_TABLE (MOD_FF_REG_5) },
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{ "pushU", { stackEv }, 0 },
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{ Bad_Opcode },
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@ -14296,6 +14301,15 @@ case_L:
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if (!(rex & REX_W))
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used_prefixes |= (prefixes & PREFIX_DATA);
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break;
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case '&':
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if (!intel_syntax
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&& address_mode == mode_64bit
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&& isa64 == intel64)
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{
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*obufp++ = 'q';
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break;
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}
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/* Fall through. */
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case 'T':
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if (!intel_syntax
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&& address_mode == mode_64bit
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@ -14816,6 +14830,12 @@ intel_operand_size (int bytemode, int sizeflag)
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case dqw_swap_mode:
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oappend ("WORD PTR ");
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break;
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case indir_v_mode:
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if (address_mode == mode_64bit && isa64 == intel64)
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{
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oappend ("QWORD PTR ");
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break;
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}
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case stack_v_mode:
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if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
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{
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@ -15193,6 +15213,12 @@ OP_E_register (int bytemode, int sizeflag)
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case bnd_mode:
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names = names_bnd;
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break;
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case indir_v_mode:
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if (address_mode == mode_64bit && isa64 == intel64)
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{
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names = names64;
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break;
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}
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case stack_v_mode:
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if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
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{
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@ -322,7 +322,8 @@ call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|N
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call, 1, 0xe8, None, 1, Cpu64, AMD64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32S }
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call, 1, 0xe8, None, 1, Cpu64, Intel64|JumpDword|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp32S }
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call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
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call, 1, 0xff, 0x2, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
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call, 1, 0xff, 0x2, 1, Cpu64, AMD64|Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
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call, 1, 0xff, 0x2, 1, Cpu64, Intel64|Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
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// Intel Syntax
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call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
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// Intel Syntax
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@ -334,7 +335,8 @@ jmp, 1, 0xeb, None, 1, CpuNo64, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_
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jmp, 1, 0xeb, None, 1, Cpu64, AMD64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32S }
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jmp, 1, 0xeb, None, 1, Cpu64, Intel64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp32S }
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jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
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jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
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jmp, 1, 0xff, 0x4, 1, Cpu64, AMD64|Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
|
||||
jmp, 1, 0xff, 0x4, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
|
||||
// Intel Syntax.
|
||||
jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
|
||||
// Intel Syntax.
|
||||
|
|
|
|||
|
|
@ -3230,10 +3230,23 @@ const insn_template i386_optab[] =
|
|||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0,
|
||||
1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0 },
|
||||
0, 0, 1, 0 },
|
||||
{ { { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
|
||||
{ "call", 1, 0xff, 0x2, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
|
||||
1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1 },
|
||||
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
|
||||
{ "call", 2, 0x9a, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -3353,10 +3366,23 @@ const insn_template i386_optab[] =
|
|||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0 },
|
||||
0, 0, 1, 0 },
|
||||
{ { { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,
|
||||
1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
|
||||
{ "jmp", 1, 0xff, 0x4, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1 },
|
||||
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } },
|
||||
{ "jmp", 2, 0xea, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue