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PR 10288

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* arm-dis.c (enum opcode_sentinels): New:  Used to mark the
        boundary between variaant and generic coprocessor instuctions.
        (coprocessor): Use it.
        Fix architecture version of MCRR and MRRC instructions.
        (arm_opcdes): Fix patterns for STRB and STRH instructions.
        (print_insn_coprocessor): Check architecture and extension masks.
        Print a hexadecimal version of any decimal constant that is
        outside of the range of -16 to +32.
        (print_arm_address): Add a return value of the offset used in the
        adress, if it is worth printing a hexadecimal version of it.
        (print_insn_neon): Print a hexadecimal version of any decimal
        constant that is outside of the range of -16 to +32.
        (print_insn_arm): Likewise.
        (print_insn_thumb16): Likewise.
        (print_insn_thumb32): Likewise.

        PR 10297
        * arm-dis.c (UNDEFINED_INSTRUCTION): New macro for a description
        of an undefined instruction.
        (arm_opcodes): Use it.
        (thumb_opcod): Use it.
        (thumb32_opc): Use it.

        Update expected disassembly regrexps in GAS and LD testsuites.
This commit is contained in:
Nick Clifton 2009-06-29 08:08:15 +00:00
parent a590713d04
commit 05413229fd
43 changed files with 1103 additions and 926 deletions
Download patch file Download diff file Expand all files Collapse all files

29
gas/testsuite/ChangeLog
View file

@ -1,3 +1,32 @@
2009-06-29 Nick Clifton <nickc@redhat.com>
PR 10288
* gas/arm/arch6zk.d: Update expected disassembly.
* gas/arm/arch7.d: Likewise.
* gas/arm/arm-it-auto-2.d: Likewise.
* gas/arm/arm-it-auto.d: Likewise.
* gas/arm/copro.d: Likewise.
* gas/arm/float.d: Likewise.
* gas/arm/fpa-mem.d: Likewise.
* gas/arm/group-reloc-ldc.d: Likewise.
* gas/arm/group-reloc-ldr.d: Likewise.
* gas/arm/iwmmxt.d: Likewise.
* gas/arm/maverick.d: Likewise.
* gas/arm/neon-omit.d: Likewise.
* gas/arm/svc.d: Likewise.
* gas/arm/thumb-eabi.d: Likewise.
* gas/arm/thumb.d: Likewise.
* gas/arm/thumb1_unified.d: Likewise.
* gas/arm/thumb2_add.d: Likewise.
* gas/arm/thumb2_relax.d: Likewise.
* gas/arm/thumb32.d: Likewise.
* gas/arm/vfp-neon-syntax.d: Likewise.
* gas/arm/vfp-neon-syntax_t2.d: Likewise.
* gas/arm/vfp1xD.d: Likewise.
* gas/arm/vfp1xD_t2.d: Likewise.
* gas/arm/vfpv3-const-conv.d: Likewise.
* gas/arm/xscale.d: Likewise.
2009-06-22 Daniel Gutson <dgutson@codesourcery.com>
* gas/arm/arm-it-auto.d: New test.

4
gas/testsuite/gas/arm/arch6zk.d
View file

@ -12,8 +12,8 @@ Disassembly of section .text:
0+010 <[^>]*> 11b4cf9f ? ldrexdne ip, \[r4\]
0+014 <[^>]*> e1fc4f9f ? ldrexh r4, \[ip\]
0+018 <[^>]*> 11f4cf9f ? ldrexhne ip, \[r4\]
0+01c <[^>]*> e320f080 ? nop \{128\}
0+020 <[^>]*> 1320f07f ? nopne \{127\}
0+01c <[^>]*> e320f080 ? nop \{128\}.*
0+020 <[^>]*> 1320f07f ? nopne \{127\}.*
0+024 <[^>]*> e320f004 ? sev
0+028 <[^>]*> e1c74f9c ? strexb r4, ip, \[r7\]
0+02c <[^>]*> 11c8cf94 ? strexbne ip, r4, \[r8\]

6
gas/testsuite/gas/arm/arch7.d
View file

@ -9,8 +9,8 @@ Disassembly of section .text:
0+004 <[^>]*> f6d9f007 pli \[r9, r7\]
0+008 <[^>]*> f6d0f101 pli \[r0, r1, lsl #2\]
0+00c <[^>]*> f4d5f000 pli \[r5\]
0+010 <[^>]*> f4d5ffff pli \[r5, #4095\]
0+014 <[^>]*> f455ffff pli \[r5, #-4095\]
0+010 <[^>]*> f4d5ffff pli \[r5, #4095\].*
0+014 <[^>]*> f455ffff pli \[r5, #-4095\].*
0+018 <[^>]*> e320f0f0 dbg #0
0+01c <[^>]*> e320f0ff dbg #15
0+020 <[^>]*> f57ff05f dmb sy
@ -26,7 +26,7 @@ Disassembly of section .text:
0+048 <[^>]*> f919 f007 pli \[r9, r7\]
0+04c <[^>]*> f910 f021 pli \[r0, r1, lsl #2\]
0+050 <[^>]*> f995 f000 pli \[r5\]
0+054 <[^>]*> f995 ffff pli \[r5, #4095\]
0+054 <[^>]*> f995 ffff pli \[r5, #4095\].*
0+058 <[^>]*> f915 fcff pli \[r5, #-255\]
0+05c <[^>]*> f99f ffff pli \[pc, #4095\] ; 0+0105f <[^>]*>
0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] ; f+ff065 <[^>]*>

2
gas/testsuite/gas/arm/arm-it-auto-2.d
View file

@ -6,7 +6,7 @@
.*: +file format .*arm.*
Disassembly of section .text:
00000000 <.text> 3a40 subs r2, #64
00000000 <.text> 3a40 subs r2, #64.*
00000002 <.text\+0x2> bfa1 itttt ge
00000004 <.text\+0x4> e8a0 500a stmiage.w r0!, {r1, r3, ip, lr}
00000008 <.text\+0x8> e8a0 500a stmiage.w r0!, {r1, r3, ip, lr}

2
gas/testsuite/gas/arm/arm-it-auto.d
View file

@ -34,7 +34,7 @@ Disassembly of section .text:
00000040 <main\+0x40> bfb8 it lt
00000042 <main\+0x42> f000 f828 bllt 00000096 <main\+0x96>
00000046 <main\+0x46> bf17 itett ne
00000048 <main\+0x48> 202d movne r0, #45
00000048 <main\+0x48> 202d movne r0, #45.*
0000004a <main\+0x4a> 2005 moveq r0, #5
0000004c <main\+0x4c> 2006 movne r0, #6
0000004e <main\+0x4e> 4487 addne pc, r0

12
gas/testsuite/gas/arm/copro.d
View file

@ -11,13 +11,13 @@ Disassembly of section .text:
0+004 <[^>]*> 0e3414a5 cfadddeq mvd1, mvd4, mvd5
0+008 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\]
0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\]
0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!
0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64
0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.*
0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64.*
0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\]
0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\]
0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\]
0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!
0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48
0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!.*
0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.*
0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\]
0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\}
0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, pc, cr1, cr2, \{7\}
@ -31,8 +31,8 @@ Disassembly of section .text:
0+054 <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\}
0+058 <[^>]*> fcd61906 ldc2l 9, cr1, \[r6\], \{6\}
0+05c <[^>]*> fcc70a07 stc2l 10, cr0, \[r7\], \{7\}
0+060 <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\}
0+064 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\}
0+060 <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\}.*
0+064 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\}.*
0+068 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4
0+06c <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5
0+070 <[^>]*> ec507fff mrrc 15, 15, r7, r0, cr15

12
gas/testsuite/gas/arm/float.d
View file

@ -121,11 +121,11 @@ Disassembly of section .text:
0+1c4 <[^>]+> eef4f11d ? cnfe f4, #5\.0
0+1c8 <[^>]+> ed900200 ? lfm f0, 4, \[r0\]
0+1cc <[^>]+> ed900200 ? lfm f0, 4, \[r0\]
0+1d0 <[^>]+> ed911210 ? lfm f1, 4, \[r1, #64\]
0+1d4 <[^>]+> edae22ff ? sfm f2, 4, \[lr, #1020\]!
0+1d8 <[^>]+> 0c68f2ff ? sfmeq f7, 3, \[r8\], #-1020
0+1d0 <[^>]+> ed911210 ? lfm f1, 4, \[r1, #64\].*
0+1d4 <[^>]+> edae22ff ? sfm f2, 4, \[lr, #1020\]!.*
0+1d8 <[^>]+> 0c68f2ff ? sfmeq f7, 3, \[r8\], #-1020.*
0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\]
0+1e0 <[^>]+> eca8f203 ? sfm f7, 1, \[r8\], #12
0+1e4 <[^>]+> 0d16520c ? lfmeq f5, 4, \[r6, #-48\]
0+1e8 <[^>]+> 1d42c209 ? sfmne f4, 3, \[r2, #-36\]
0+1ec <[^>]+> 1d62c209 ? sfmne f4, 3, \[r2, #-36\]!
0+1e4 <[^>]+> 0d16520c ? lfmeq f5, 4, \[r6, #-48\].*
0+1e8 <[^>]+> 1d42c209 ? sfmne f4, 3, \[r2, #-36\].*
0+1ec <[^>]+> 1d62c209 ? sfmne f4, 3, \[r2, #-36\]!.*

4
gas/testsuite/gas/arm/fpa-mem.d
View file

@ -26,9 +26,9 @@ Disassembly of section .text:
0+3c <[^>]*> ec608101 ? stfp f0, \[r0\], #-4
0+40 <[^>]*> ed900200 ? lfm f0, 4, \[r0\]
0+44 <[^>]*> ed900200 ? lfm f0, 4, \[r0\]
0+48 <[^>]*> ed10020c ? lfm f0, 4, \[r0, #-48\]
0+48 <[^>]*> ed10020c ? lfm f0, 4, \[r0, #-48\].*
0+4c <[^>]*> ed800200 ? sfm f0, 4, \[r0\]
0+50 <[^>]*> ed00020c ? sfm f0, 4, \[r0, #-48\]
0+50 <[^>]*> ed00020c ? sfm f0, 4, \[r0, #-48\].*
0+54 <[^>]*> ed800200 ? sfm f0, 4, \[r0\]
0+58 <[^>]*> 5d800100 ? stfpls f0, \[r0\]
0+5c <[^>]*> 5d800100 ? stfpls f0, \[r0\]

720
gas/testsuite/gas/arm/group-reloc-ldc.d
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File diff suppressed because it is too large Load diff

192
gas/testsuite/gas/arm/group-reloc-ldr.d
View file

@ -5,196 +5,196 @@
.*: +file format .*arm.*
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
0: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
4: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
8: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
c: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
10: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
14: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
18: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
1c: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
20: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
24: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
28: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
2c: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
30: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
34: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
38: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
3c: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
40: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
44: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
48: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
4c: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
50: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
54: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
58: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
5c: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
60: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
64: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
68: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
6c: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
70: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
74: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
78: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
7c: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
80: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
84: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
88: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
8c: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
90: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
94: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
98: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
9c: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
a0: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
a4: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
a8: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
ac: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
b0: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
b4: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
b8: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
bc: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
c0: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
c4: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
c8: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
cc: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
d0: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].*
d4: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
d8: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
dc: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
e0: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
e4: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
e8: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].*
ec: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
f0: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
f4: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
f8: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
fc: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
100: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].*
104: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
108: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
10c: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
110: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
114: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
118: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].*
11c: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
120: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
124: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
128: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
12c: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
130: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].*
134: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
138: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
13c: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
140: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
144: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
148: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].*
14c: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
150: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
154: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
158: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
15c: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
160: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].*
164: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
168: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
16c: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
170: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
174: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
178: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].*
17c: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0

6
gas/testsuite/gas/arm/iwmmxt.d
View file

@ -74,7 +74,7 @@ Disassembly of section .text:
0+108 <[^>]*> ed901024[ ]+wldrb[ ]+wr1, \[r0, #36\]
0+10c <[^>]*> 0df12018[ ]+wldrheq[ ]+wr2, \[r1, #24\]!
0+110 <[^>]*> 1cb23104[ ]+wldrwne[ ]+wr3, \[r2\], #16
0+114 <[^>]*> 6d534153[ ]+wldrdvs[ ]+wr4, \[r3, #-332\]
0+114 <[^>]*> 6d534153[ ]+wldrdvs[ ]+wr4, \[r3, #-332\].*
0+118 <[^>]*> fdb12105[ ]+wldrw[ ]+wcssf, \[r1, #20\]!
0+11c <[^>]*> ee474109[ ]+wmacu[ ]+wr4, wr7, wr9
0+120 <[^>]*> 2e6a810e[ ]+wmacscs[ ]+wr8, wr10, wr14
@ -138,8 +138,8 @@ Disassembly of section .text:
0+208 <[^>]*> ed8110ff[ ]+wstrb[ ]+wr1, \[r1, #255\]
0+20c <[^>]*> ed6110ff[ ]+wstrh[ ]+wr1, \[r1, #-255\]!
0+210 <[^>]*> eca11101[ ]+wstrw[ ]+wr1, \[r1\], #4
0+214 <[^>]*> edc111ff[ ]+wstrd[ ]+wr1, \[r1, #1020\]
0+218 <[^>]*> fca1314b[ ]+wstrw[ ]+wcasf, \[r1\], #300
0+214 <[^>]*> edc111ff[ ]+wstrd[ ]+wr1, \[r1, #1020\].*
0+218 <[^>]*> fca1314b[ ]+wstrw[ ]+wcasf, \[r1\], #300.*
0+21c <[^>]*> 3e1311ae[ ]+wsubbuscc[ ]+wr1, wr3, wr14
0+220 <[^>]*> ee5311ae[ ]+wsubhus[ ]+wr1, wr3, wr14
0+224 <[^>]*> 3e9311ae[ ]+wsubwuscc[ ]+wr1, wr3, wr14

248
gas/testsuite/gas/arm/maverick.d
View file

@ -8,126 +8,126 @@
Disassembly of section .text:
# load_store:
0*0 <load_store> 0d ?9d ?54 ?ff ? * cfldrseq mvf5, ?\[sp, #1020\]
0*4 <load_store\+0x4> 4d ?9b ?e4 ?49 ? * cfldrsmi mvf14, ?\[fp, #292\]
0*8 <load_store\+0x8> 7d ?1c ?24 ?ef ? * cfldrsvc mvf2, ?\[ip, #-956\]
0*c <load_store\+0xc> bd ?1a ?04 ?ff ? * cfldrslt mvf0, ?\[sl, #-1020\]
0*10 <load_store\+0x10> 3d ?11 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1, #-156\]
0*14 <load_store\+0x14> ed ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9, #416\]!
0*18 <load_store\+0x18> 2d ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0, #-1020\]!
0*1c <load_store\+0x1c> 9d ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1, #-156\]!
0*20 <load_store\+0x20> dd ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9, #416\]!
0*24 <load_store\+0x24> 6d ?30 ?b4 ?ff ? * cfldrsvs mvf11, ?\[r0, #-1020\]!
0*28 <load_store\+0x28> 3c ?31 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1\], #-156
0*2c <load_store\+0x2c> ec ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9\], #416
0*30 <load_store\+0x30> 2c ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0\], #-1020
0*34 <load_store\+0x34> 9c ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1\], #-156
0*38 <load_store\+0x38> dc ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9\], #416
0*3c <load_store\+0x3c> 6d ?50 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\]
0*40 <load_store\+0x40> 3d ?51 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\]
0*44 <load_store\+0x44> ed ?d9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\]
0*48 <load_store\+0x48> 2d ?50 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\]
0*4c <load_store\+0x4c> 9d ?51 ?44 ?27 ? * cfldrdls mvd4, ?\[r1, #-156\]
0*50 <load_store\+0x50> dd ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9, #416\]!
0*54 <load_store\+0x54> 6d ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\]!
0*58 <load_store\+0x58> 3d ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\]!
0*5c <load_store\+0x5c> ed ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\]!
0*60 <load_store\+0x60> 2d ?70 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\]!
0*64 <load_store\+0x64> 9c ?71 ?44 ?27 ? * cfldrdls mvd4, ?\[r1\], #-156
0*68 <load_store\+0x68> dc ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9\], #416
0*6c <load_store\+0x6c> 6c ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0\], #-1020
0*70 <load_store\+0x70> 3c ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1\], #-156
0*74 <load_store\+0x74> ec ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9\], #416
0*78 <load_store\+0x78> 2d ?10 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\]
0*7c <load_store\+0x7c> 9d ?11 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\]
0*80 <load_store\+0x80> dd ?99 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\]
0*84 <load_store\+0x84> 6d ?10 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\]
0*88 <load_store\+0x88> 3d ?11 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1, #-156\]
0*8c <load_store\+0x8c> ed ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9, #416\]!
0*90 <load_store\+0x90> 2d ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\]!
0*94 <load_store\+0x94> 9d ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\]!
0*98 <load_store\+0x98> dd ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\]!
0*9c <load_store\+0x9c> 6d ?30 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\]!
0*a0 <load_store\+0xa0> 3c ?31 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1\], #-156
0*a4 <load_store\+0xa4> ec ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9\], #416
0*a8 <load_store\+0xa8> 2c ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0\], #-1020
0*ac <load_store\+0xac> 9c ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1\], #-156
0*b0 <load_store\+0xb0> dc ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9\], #416
0*b4 <load_store\+0xb4> 6d ?50 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\]
0*b8 <load_store\+0xb8> 3d ?51 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\]
0*bc <load_store\+0xbc> ed ?d9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\]
0*c0 <load_store\+0xc0> 2d ?50 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\]
0*c4 <load_store\+0xc4> 9d ?51 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1, #-156\]
0*c8 <load_store\+0xc8> dd ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9, #416\]!
0*cc <load_store\+0xcc> 6d ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\]!
0*d0 <load_store\+0xd0> 3d ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\]!
0*d4 <load_store\+0xd4> ed ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\]!
0*d8 <load_store\+0xd8> 2d ?70 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\]!
0*dc <load_store\+0xdc> 9c ?71 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1\], #-156
0*e0 <load_store\+0xe0> dc ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9\], #416
0*e4 <load_store\+0xe4> 6c ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0\], #-1020
0*e8 <load_store\+0xe8> 3c ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1\], #-156
0*ec <load_store\+0xec> ec ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9\], #416
0*f0 <load_store\+0xf0> 2d ?00 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\]
0*f4 <load_store\+0xf4> 9d ?01 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\]
0*f8 <load_store\+0xf8> dd ?89 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\]
0*fc <load_store\+0xfc> 6d ?00 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\]
0*100 <load_store\+0x100> 3d ?01 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1, #-156\]
0*104 <load_store\+0x104> ed ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9, #416\]!
0*108 <load_store\+0x108> 2d ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\]!
0*10c <load_store\+0x10c> 9d ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\]!
0*110 <load_store\+0x110> dd ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\]!
0*114 <load_store\+0x114> 6d ?20 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\]!
0*118 <load_store\+0x118> 3c ?21 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1\], #-156
0*11c <load_store\+0x11c> ec ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9\], #416
0*120 <load_store\+0x120> 2c ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0\], #-1020
0*124 <load_store\+0x124> 9c ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1\], #-156
0*128 <load_store\+0x128> dc ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9\], #416
0*12c <load_store\+0x12c> 6d ?40 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\]
0*130 <load_store\+0x130> 3d ?41 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\]
0*134 <load_store\+0x134> ed ?c9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\]
0*138 <load_store\+0x138> 2d ?40 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\]
0*13c <load_store\+0x13c> 9d ?41 ?44 ?27 ? * cfstrdls mvd4, ?\[r1, #-156\]
0*140 <load_store\+0x140> dd ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9, #416\]!
0*144 <load_store\+0x144> 6d ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\]!
0*148 <load_store\+0x148> 3d ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\]!
0*14c <load_store\+0x14c> ed ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\]!
0*150 <load_store\+0x150> 2d ?60 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\]!
0*154 <load_store\+0x154> 9c ?61 ?44 ?27 ? * cfstrdls mvd4, ?\[r1\], #-156
0*158 <load_store\+0x158> dc ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9\], #416
0*15c <load_store\+0x15c> 6c ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0\], #-1020
0*160 <load_store\+0x160> 3c ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1\], #-156
0*164 <load_store\+0x164> ec ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9\], #416
0*168 <load_store\+0x168> 2d ?00 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\]
0*16c <load_store\+0x16c> 9d ?01 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\]
0*170 <load_store\+0x170> dd ?89 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\]
0*174 <load_store\+0x174> 6d ?00 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\]
0*178 <load_store\+0x178> 3d ?01 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1, #-156\]
0*17c <load_store\+0x17c> ed ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9, #416\]!
0*180 <load_store\+0x180> 2d ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\]!
0*184 <load_store\+0x184> 9d ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\]!
0*188 <load_store\+0x188> dd ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\]!
0*18c <load_store\+0x18c> 6d ?20 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\]!
0*190 <load_store\+0x190> 3c ?21 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1\], #-156
0*194 <load_store\+0x194> ec ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9\], #416
0*198 <load_store\+0x198> 2c ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0\], #-1020
0*19c <load_store\+0x19c> 9c ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1\], #-156
0*1a0 <load_store\+0x1a0> dc ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9\], #416
0*1a4 <load_store\+0x1a4> 6d ?40 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\]
0*1a8 <load_store\+0x1a8> 3d ?41 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\]
0*1ac <load_store\+0x1ac> ed ?c9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\]
0*1b0 <load_store\+0x1b0> 2d ?40 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\]
0*1b4 <load_store\+0x1b4> 9d ?41 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1, #-156\]
0*1b8 <load_store\+0x1b8> dd ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9, #416\]!
0*1bc <load_store\+0x1bc> 6d ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\]!
0*1c0 <load_store\+0x1c0> 3d ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\]!
0*1c4 <load_store\+0x1c4> ed ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\]!
0*1c8 <load_store\+0x1c8> 2d ?60 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\]!
0*1cc <load_store\+0x1cc> 9c ?61 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1\], #-156
0*1d0 <load_store\+0x1d0> dc ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9\], #416
0*1d4 <load_store\+0x1d4> 6c ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0\], #-1020
0*1d8 <load_store\+0x1d8> 3c ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1\], #-156
0*1dc <load_store\+0x1dc> ec ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9\], #416
0*0 <load_store> 0d ?9d ?54 ?ff ? * cfldrseq mvf5, ?\[sp, #1020\].*
0*4 <load_store\+0x4> 4d ?9b ?e4 ?49 ? * cfldrsmi mvf14, ?\[fp, #292\].*
0*8 <load_store\+0x8> 7d ?1c ?24 ?ef ? * cfldrsvc mvf2, ?\[ip, #-956\].*
0*c <load_store\+0xc> bd ?1a ?04 ?ff ? * cfldrslt mvf0, ?\[sl, #-1020\].*
0*10 <load_store\+0x10> 3d ?11 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1, #-156\].*
0*14 <load_store\+0x14> ed ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9, #416\]!.*
0*18 <load_store\+0x18> 2d ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0, #-1020\]!.*
0*1c <load_store\+0x1c> 9d ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1, #-156\]!.*
0*20 <load_store\+0x20> dd ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9, #416\]!.*
0*24 <load_store\+0x24> 6d ?30 ?b4 ?ff ? * cfldrsvs mvf11, ?\[r0, #-1020\]!.*
0*28 <load_store\+0x28> 3c ?31 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1\], #-156.*
0*2c <load_store\+0x2c> ec ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9\], #416.*
0*30 <load_store\+0x30> 2c ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0\], #-1020.*
0*34 <load_store\+0x34> 9c ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1\], #-156.*
0*38 <load_store\+0x38> dc ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9\], #416.*
0*3c <load_store\+0x3c> 6d ?50 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\].*
0*40 <load_store\+0x40> 3d ?51 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\].*
0*44 <load_store\+0x44> ed ?d9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\].*
0*48 <load_store\+0x48> 2d ?50 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\].*
0*4c <load_store\+0x4c> 9d ?51 ?44 ?27 ? * cfldrdls mvd4, ?\[r1, #-156\].*
0*50 <load_store\+0x50> dd ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9, #416\]!.*
0*54 <load_store\+0x54> 6d ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\]!.*
0*58 <load_store\+0x58> 3d ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\]!.*
0*5c <load_store\+0x5c> ed ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\]!.*
0*60 <load_store\+0x60> 2d ?70 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\]!.*
0*64 <load_store\+0x64> 9c ?71 ?44 ?27 ? * cfldrdls mvd4, ?\[r1\], #-156.*
0*68 <load_store\+0x68> dc ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9\], #416.*
0*6c <load_store\+0x6c> 6c ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0\], #-1020.*
0*70 <load_store\+0x70> 3c ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1\], #-156.*
0*74 <load_store\+0x74> ec ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9\], #416.*
0*78 <load_store\+0x78> 2d ?10 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\].*
0*7c <load_store\+0x7c> 9d ?11 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\].*
0*80 <load_store\+0x80> dd ?99 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\].*
0*84 <load_store\+0x84> 6d ?10 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\].*
0*88 <load_store\+0x88> 3d ?11 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1, #-156\].*
0*8c <load_store\+0x8c> ed ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9, #416\]!.*
0*90 <load_store\+0x90> 2d ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\]!.*
0*94 <load_store\+0x94> 9d ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\]!.*
0*98 <load_store\+0x98> dd ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\]!.*
0*9c <load_store\+0x9c> 6d ?30 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\]!.*
0*a0 <load_store\+0xa0> 3c ?31 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1\], #-156.*
0*a4 <load_store\+0xa4> ec ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9\], #416.*
0*a8 <load_store\+0xa8> 2c ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0\], #-1020.*
0*ac <load_store\+0xac> 9c ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1\], #-156.*
0*b0 <load_store\+0xb0> dc ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9\], #416.*
0*b4 <load_store\+0xb4> 6d ?50 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\].*
0*b8 <load_store\+0xb8> 3d ?51 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\].*
0*bc <load_store\+0xbc> ed ?d9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\].*
0*c0 <load_store\+0xc0> 2d ?50 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\].*
0*c4 <load_store\+0xc4> 9d ?51 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1, #-156\].*
0*c8 <load_store\+0xc8> dd ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9, #416\]!.*
0*cc <load_store\+0xcc> 6d ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\]!.*
0*d0 <load_store\+0xd0> 3d ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\]!.*
0*d4 <load_store\+0xd4> ed ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\]!.*
0*d8 <load_store\+0xd8> 2d ?70 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\]!.*
0*dc <load_store\+0xdc> 9c ?71 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1\], #-156.*
0*e0 <load_store\+0xe0> dc ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9\], #416.*
0*e4 <load_store\+0xe4> 6c ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0\], #-1020.*
0*e8 <load_store\+0xe8> 3c ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1\], #-156.*
0*ec <load_store\+0xec> ec ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9\], #416.*
0*f0 <load_store\+0xf0> 2d ?00 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\].*
0*f4 <load_store\+0xf4> 9d ?01 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\].*
0*f8 <load_store\+0xf8> dd ?89 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\].*
0*fc <load_store\+0xfc> 6d ?00 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\].*
0*100 <load_store\+0x100> 3d ?01 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1, #-156\].*
0*104 <load_store\+0x104> ed ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9, #416\]!.*
0*108 <load_store\+0x108> 2d ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\]!.*
0*10c <load_store\+0x10c> 9d ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\]!.*
0*110 <load_store\+0x110> dd ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\]!.*
0*114 <load_store\+0x114> 6d ?20 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\]!.*
0*118 <load_store\+0x118> 3c ?21 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1\], #-156.*
0*11c <load_store\+0x11c> ec ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9\], #416.*
0*120 <load_store\+0x120> 2c ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0\], #-1020.*
0*124 <load_store\+0x124> 9c ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1\], #-156.*
0*128 <load_store\+0x128> dc ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9\], #416.*
0*12c <load_store\+0x12c> 6d ?40 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\].*
0*130 <load_store\+0x130> 3d ?41 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\].*
0*134 <load_store\+0x134> ed ?c9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\].*
0*138 <load_store\+0x138> 2d ?40 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\].*
0*13c <load_store\+0x13c> 9d ?41 ?44 ?27 ? * cfstrdls mvd4, ?\[r1, #-156\].*
0*140 <load_store\+0x140> dd ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9, #416\]!.*
0*144 <load_store\+0x144> 6d ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\]!.*
0*148 <load_store\+0x148> 3d ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\]!.*
0*14c <load_store\+0x14c> ed ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\]!.*
0*150 <load_store\+0x150> 2d ?60 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\]!.*
0*154 <load_store\+0x154> 9c ?61 ?44 ?27 ? * cfstrdls mvd4, ?\[r1\], #-156.*
0*158 <load_store\+0x158> dc ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9\], #416.*
0*15c <load_store\+0x15c> 6c ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0\], #-1020.*
0*160 <load_store\+0x160> 3c ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1\], #-156.*
0*164 <load_store\+0x164> ec ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9\], #416.*
0*168 <load_store\+0x168> 2d ?00 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\].*
0*16c <load_store\+0x16c> 9d ?01 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\].*
0*170 <load_store\+0x170> dd ?89 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\].*
0*174 <load_store\+0x174> 6d ?00 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\].*
0*178 <load_store\+0x178> 3d ?01 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1, #-156\].*
0*17c <load_store\+0x17c> ed ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9, #416\]!.*
0*180 <load_store\+0x180> 2d ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\]!.*
0*184 <load_store\+0x184> 9d ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\]!.*
0*188 <load_store\+0x188> dd ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\]!.*
0*18c <load_store\+0x18c> 6d ?20 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\]!.*
0*190 <load_store\+0x190> 3c ?21 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1\], #-156.*
0*194 <load_store\+0x194> ec ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9\], #416.*
0*198 <load_store\+0x198> 2c ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0\], #-1020.*
0*19c <load_store\+0x19c> 9c ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1\], #-156.*
0*1a0 <load_store\+0x1a0> dc ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9\], #416.*
0*1a4 <load_store\+0x1a4> 6d ?40 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\].*
0*1a8 <load_store\+0x1a8> 3d ?41 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\].*
0*1ac <load_store\+0x1ac> ed ?c9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\].*
0*1b0 <load_store\+0x1b0> 2d ?40 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\].*
0*1b4 <load_store\+0x1b4> 9d ?41 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1, #-156\].*
0*1b8 <load_store\+0x1b8> dd ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9, #416\]!.*
0*1bc <load_store\+0x1bc> 6d ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\]!.*
0*1c0 <load_store\+0x1c0> 3d ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\]!.*
0*1c4 <load_store\+0x1c4> ed ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\]!.*
0*1c8 <load_store\+0x1c8> 2d ?60 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\]!.*
0*1cc <load_store\+0x1cc> 9c ?61 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1\], #-156.*
0*1d0 <load_store\+0x1d0> dc ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9\], #416.*
0*1d4 <load_store\+0x1d4> 6c ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0\], #-1020.*
0*1d8 <load_store\+0x1d8> 3c ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1\], #-156.*
0*1dc <load_store\+0x1dc> ec ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9\], #416.*
# move:
0*1e0 <move> 2e ?09 ?04 ?50 ? * cfmvsrcs mvf9, ?r0
0*1e4 <move\+0x4> 5e ?0f ?74 ?50 ? * cfmvsrpl mvf15, ?r7
@ -313,13 +313,13 @@ Disassembly of section .text:
0*4ac <shift\+0x24> de ?07 ?c5 ?72 ? * cfrshl64le mvdx7, ?mvdx2, ?ip
0*4b0 <shift\+0x28> 6e ?00 ?b5 ?ef ? * cfsh32vs mvfx11, ?mvfx0, ?#-1
0*4b4 <shift\+0x2c> ee ?0c ?35 ?28 ? * cfsh32 mvfx3, ?mvfx12, ?#24
0*4b8 <shift\+0x30> 8e ?0d ?f5 ?41 ? * cfsh32hi mvfx15, ?mvfx13, ?#33
0*4b8 <shift\+0x30> 8e ?0d ?f5 ?41 ? * cfsh32hi mvfx15, ?mvfx13, ?#33.*
0*4bc <shift\+0x34> 4e ?09 ?25 ?00 ? * cfsh32mi mvfx2, ?mvfx9, ?#0
0*4c0 <shift\+0x38> ee ?09 ?a5 ?40 ? * cfsh32 mvfx10, ?mvfx9, ?#32
0*4c4 <shift\+0x3c> 3e ?2d ?85 ?c1 ? * cfsh64cc mvdx8, ?mvdx13, ?#-31
0*4c4 <shift\+0x3c> 3e ?2d ?85 ?c1 ? * cfsh64cc mvdx8, ?mvdx13, ?#-31.*
0*4c8 <shift\+0x40> 1e ?26 ?c5 ?01 ? * cfsh64ne mvdx12, ?mvdx6, ?#1
0*4cc <shift\+0x44> 7e ?2e ?55 ?c0 ? * cfsh64vc mvdx5, ?mvdx14, ?#-32
0*4d0 <shift\+0x48> ae ?28 ?15 ?c5 ? * cfsh64ge mvdx1, ?mvdx8, ?#-27
0*4cc <shift\+0x44> 7e ?2e ?55 ?c0 ? * cfsh64vc mvdx5, ?mvdx14, ?#-32.*
0*4d0 <shift\+0x48> ae ?28 ?15 ?c5 ? * cfsh64ge mvdx1, ?mvdx8, ?#-27.*
0*4d4 <shift\+0x4c> 6e ?24 ?b5 ?eb ? * cfsh64vs mvdx11, ?mvdx4, ?#-5
# comp:
0*4d8 <comp> 0e ?1f ?a4 ?9a ? * cfcmpseq sl, ?mvf15, ?mvf10

4
gas/testsuite/gas/arm/neon-omit.d
View file

@ -49,7 +49,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f39a6156 vsra\.u16 q3, q3, #6
0[0-9a-f]+ <[^>]+> f39a8358 vrsra\.u16 q4, q4, #6
0[0-9a-f]+ <[^>]+> f3954554 vsli\.16 q2, q2, #5
0[0-9a-f]+ <[^>]+> f3bff69f vqshlu\.s64 d15, d15, #63
0[0-9a-f]+ <[^>]+> f3bff69f vqshlu\.s64 d15, d15, #63.*
0[0-9a-f]+ <[^>]+> f2b55306 vext\.8 d5, d5, d6, #3
0[0-9a-f]+ <[^>]+> f3042746 vabd\.u8 q1, q2, q3
0[0-9a-f]+ <[^>]+> f262c0c6 vhadd\.s32 q14, q9, q3
@ -91,5 +91,5 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f39a6152 vsra\.u16 q3, q1, #6
0[0-9a-f]+ <[^>]+> f3dae358 vrsra\.u16 q15, q4, #6
0[0-9a-f]+ <[^>]+> f3954556 vsli\.16 q2, q3, #5
0[0-9a-f]+ <[^>]+> f3bff6b7 vqshlu\.s64 d15, d23, #63
0[0-9a-f]+ <[^>]+> f3bff6b7 vqshlu\.s64 d15, d23, #63.*
0[0-9a-f]+ <[^>]+> f2b25386 vext\.8 d5, d18, d6, #3

8
gas/testsuite/gas/arm/svc.d
View file

@ -8,7 +8,7 @@ Disassembly of section \.text:
0+004 <[^>]+> ef876543 (swi|svc) 0x00876543
0+008 <[^>]+> ef123456 (swi|svc) 0x00123456
0+00c <[^>]+> ef876543 (swi|svc) 0x00876543
0+010 <[^>]+> df5a (swi|svc) 90
0+012 <[^>]+> dfa5 (swi|svc) 165
0+014 <[^>]+> df5a (swi|svc) 90
0+016 <[^>]+> dfa5 (swi|svc) 165
0+010 <[^>]+> df5a (swi|svc) 90.*
0+012 <[^>]+> dfa5 (swi|svc) 165.*
0+014 <[^>]+> df5a (swi|svc) 90.*
0+016 <[^>]+> dfa5 (swi|svc) 165.*

48
gas/testsuite/gas/arm/thumb-eabi.d
View file

@ -19,10 +19,10 @@ Disassembly of section \.text:
0+012 <[^>]+> 1ca2 adds r2, r4, #2
0+014 <[^>]+> 1beb subs r3, r5, r7
0+016 <[^>]+> 1fe2 subs r2, r4, #7
0+018 <[^>]+> 24ff movs r4, #255
0+01a <[^>]+> 2bfa cmp r3, #250
0+01c <[^>]+> 367b adds r6, #123
0+01e <[^>]+> 3d80 subs r5, #128
0+018 <[^>]+> 24ff movs r4, #255.*
0+01a <[^>]+> 2bfa cmp r3, #250.*
0+01c <[^>]+> 367b adds r6, #123.*
0+01e <[^>]+> 3d80 subs r5, #128.*
0+020 <[^>]+> 402b ands r3, r5
0+022 <[^>]+> 4074 eors r4, r6
0+024 <[^>]+> 4081 lsls r1, r0
@ -63,24 +63,24 @@ Disassembly of section \.text:
0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\]
0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\]
0+06e <[^>]+> 5f42 ldrsh r2, \[r0, r5\]
0+070 <[^>]+> 67db str r3, \[r3, #124\]
0+072 <[^>]+> 6fe1 ldr r1, \[r4, #124\]
0+070 <[^>]+> 67db str r3, \[r3, #124\].*
0+072 <[^>]+> 6fe1 ldr r1, \[r4, #124\].*
0+074 <[^>]+> 682d ldr r5, \[r5, #0\]
0+076 <[^>]+> 77e9 strb r1, \[r5, #31\]
0+078 <[^>]+> 7161 strb r1, \[r4, #5\]
0+07a <[^>]+> 7032 strb r2, \[r6, #0\]
0+07c <[^>]+> 87ec strh r4, \[r5, #62\]
0+07c <[^>]+> 87ec strh r4, \[r5, #62\].*
0+07e <[^>]+> 8885 ldrh r5, \[r0, #4\]
0+080 <[^>]+> 8813 ldrh r3, \[r2, #0\]
0+082 <[^>]+> 93ff str r3, \[sp, #1020\]
0+084 <[^>]+> 990b ldr r1, \[sp, #44\]
0+082 <[^>]+> 93ff str r3, \[sp, #1020\].*
0+084 <[^>]+> 990b ldr r1, \[sp, #44\].*
0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\]
0+088 <[^>]+> a7ff add r7, pc, #1020 \(adr r7, 0+488 <[^>]+>\)
0+08a <[^>]+> ac80 add r4, sp, #512
0+08c <[^>]+> b043 add sp, #268
0+08e <[^>]+> b09a sub sp, #104
0+090 <[^>]+> b0c3 sub sp, #268
0+092 <[^>]+> b01b add sp, #108
0+08a <[^>]+> ac80 add r4, sp, #512.*
0+08c <[^>]+> b043 add sp, #268.*
0+08e <[^>]+> b09a sub sp, #104.*
0+090 <[^>]+> b0c3 sub sp, #268.*
0+092 <[^>]+> b01b add sp, #108.*
0+094 <[^>]+> b417 push {r0, r1, r2, r4}
0+096 <[^>]+> b5f9 push {r0, r3, r4, r5, r6, r7, lr}
0+098 <[^>]+> bc98 pop {r3, r4, r7}
@ -108,17 +108,17 @@ Disassembly of section \.text:
0+0c4 <[^>]+> e7d0 b.n 0+068 <[^>]+>
0+0c6 <[^>]+> 00ac lsls r4, r5, #2
0+0c8 <[^>]+> 1c9a adds r2, r3, #2
0+0ca <[^>]+> b07f add sp, #508
0+0cc <[^>]+> b0ff sub sp, #508
0+0ce <[^>]+> a8ff add r0, sp, #1020
0+0ca <[^>]+> b07f add sp, #508.*
0+0cc <[^>]+> b0ff sub sp, #508.*
0+0ce <[^>]+> a8ff add r0, sp, #1020.*
0+0d0 <[^>]+> a0ff add r0, pc, #1020 \(adr r0, 0+4d0 <[^>]+>\)
0+0d2 <[^>]+> b01a add sp, #104
0+0d4 <[^>]+> b09a sub sp, #104
0+0d6 <[^>]+> a81a add r0, sp, #104
0+0d2 <[^>]+> b01a add sp, #104.*
0+0d4 <[^>]+> b09a sub sp, #104.*
0+0d6 <[^>]+> a81a add r0, sp, #104.*
0+0d8 <[^>]+> a01a add r0, pc, #104 \(adr r0, 0+144 <[^>]+>\)
0+0da <[^>]+> 3168 adds r1, #104
0+0dc <[^>]+> 2668 movs r6, #104
0+0de <[^>]+> 2f68 cmp r7, #104
0+0da <[^>]+> 3168 adds r1, #104.*
0+0dc <[^>]+> 2668 movs r6, #104.*
0+0de <[^>]+> 2f68 cmp r7, #104.*
0+0e0 <[^>]+> 46c0 nop \(mov r8, r8\)
0+0e2 <[^>]+> 46c0 nop \(mov r8, r8\)
0+0e4 <[^>]+> eafffffe b 0+0e4 <[^>]+>
@ -134,7 +134,7 @@ Disassembly of section \.text:
0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+>
0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+>
0+10a <[^>]+> 4700 bx r0
0+10c <[^>]+> dfff (swi|svc) 255
0+10c <[^>]+> dfff (swi|svc) 255.*
0+10e <[^>]+> 46c0 nop \(mov r8, r8\)
0+110 <[^>]+> d010 beq.n 0+134 <[^>]+>
0+112 <[^>]+> d10f bne.n 0+134 <[^>]+>

48
gas/testsuite/gas/arm/thumb.d
View file

@ -20,10 +20,10 @@ Disassembly of section \.text:
0+012 <[^>]+> 1ca2 adds r2, r4, #2
0+014 <[^>]+> 1beb subs r3, r5, r7
0+016 <[^>]+> 1fe2 subs r2, r4, #7
0+018 <[^>]+> 24ff movs r4, #255
0+01a <[^>]+> 2bfa cmp r3, #250
0+01c <[^>]+> 367b adds r6, #123
0+01e <[^>]+> 3d80 subs r5, #128
0+018 <[^>]+> 24ff movs r4, #255.*
0+01a <[^>]+> 2bfa cmp r3, #250.*
0+01c <[^>]+> 367b adds r6, #123.*
0+01e <[^>]+> 3d80 subs r5, #128.*
0+020 <[^>]+> 402b ands r3, r5
0+022 <[^>]+> 4074 eors r4, r6
0+024 <[^>]+> 4081 lsls r1, r0
@ -64,24 +64,24 @@ Disassembly of section \.text:
0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\]
0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\]
0+06e <[^>]+> 5f42 ldrsh r2, \[r0, r5\]
0+070 <[^>]+> 67db str r3, \[r3, #124\]
0+072 <[^>]+> 6fe1 ldr r1, \[r4, #124\]
0+070 <[^>]+> 67db str r3, \[r3, #124\].*
0+072 <[^>]+> 6fe1 ldr r1, \[r4, #124\].*
0+074 <[^>]+> 682d ldr r5, \[r5, #0\]
0+076 <[^>]+> 77e9 strb r1, \[r5, #31\]
0+078 <[^>]+> 7161 strb r1, \[r4, #5\]
0+07a <[^>]+> 7032 strb r2, \[r6, #0\]
0+07c <[^>]+> 87ec strh r4, \[r5, #62\]
0+07c <[^>]+> 87ec strh r4, \[r5, #62\].*
0+07e <[^>]+> 8885 ldrh r5, \[r0, #4\]
0+080 <[^>]+> 8813 ldrh r3, \[r2, #0\]
0+082 <[^>]+> 93ff str r3, \[sp, #1020\]
0+084 <[^>]+> 990b ldr r1, \[sp, #44\]
0+082 <[^>]+> 93ff str r3, \[sp, #1020\].*
0+084 <[^>]+> 990b ldr r1, \[sp, #44\].*
0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\]
0+088 <[^>]+> a7ff add r7, pc, #1020 \(adr r7, 0+488 <[^>]+>\)
0+08a <[^>]+> ac80 add r4, sp, #512
0+08c <[^>]+> b043 add sp, #268
0+08e <[^>]+> b09a sub sp, #104
0+090 <[^>]+> b0c3 sub sp, #268
0+092 <[^>]+> b01b add sp, #108
0+08a <[^>]+> ac80 add r4, sp, #512.*
0+08c <[^>]+> b043 add sp, #268.*
0+08e <[^>]+> b09a sub sp, #104.*
0+090 <[^>]+> b0c3 sub sp, #268.*
0+092 <[^>]+> b01b add sp, #108.*
0+094 <[^>]+> b417 push {r0, r1, r2, r4}
0+096 <[^>]+> b5f9 push {r0, r3, r4, r5, r6, r7, lr}
0+098 <[^>]+> bc98 pop {r3, r4, r7}
@ -109,17 +109,17 @@ Disassembly of section \.text:
0+0c4 <[^>]+> e7d0 b.n 0+068 <[^>]+>
0+0c6 <[^>]+> 00ac lsls r4, r5, #2
0+0c8 <[^>]+> 1c9a adds r2, r3, #2
0+0ca <[^>]+> b07f add sp, #508
0+0cc <[^>]+> b0ff sub sp, #508
0+0ce <[^>]+> a8ff add r0, sp, #1020
0+0ca <[^>]+> b07f add sp, #508.*
0+0cc <[^>]+> b0ff sub sp, #508.*
0+0ce <[^>]+> a8ff add r0, sp, #1020.*
0+0d0 <[^>]+> a0ff add r0, pc, #1020 \(adr r0, 0+4d0 <[^>]+>\)
0+0d2 <[^>]+> b01a add sp, #104
0+0d4 <[^>]+> b09a sub sp, #104
0+0d6 <[^>]+> a81a add r0, sp, #104
0+0d2 <[^>]+> b01a add sp, #104.*
0+0d4 <[^>]+> b09a sub sp, #104.*
0+0d6 <[^>]+> a81a add r0, sp, #104.*
0+0d8 <[^>]+> a01a add r0, pc, #104 \(adr r0, 0+144 <[^>]+>\)
0+0da <[^>]+> 3168 adds r1, #104
0+0dc <[^>]+> 2668 movs r6, #104
0+0de <[^>]+> 2f68 cmp r7, #104
0+0da <[^>]+> 3168 adds r1, #104.*
0+0dc <[^>]+> 2668 movs r6, #104.*
0+0de <[^>]+> 2f68 cmp r7, #104.*
0+0e0 <[^>]+> 46c0 nop \(mov r8, r8\)
0+0e2 <[^>]+> 46c0 nop \(mov r8, r8\)
0+0e4 <[^>]+> eafffffe b 0+0e4 <[^>]+>
@ -134,7 +134,7 @@ Disassembly of section \.text:
0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+>
0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+>
0+10a <[^>]+> 4700 bx r0
0+10c <[^>]+> dfff (swi|svc) 255
0+10c <[^>]+> dfff (swi|svc) 255.*
0+10e <[^>]+> 46c0 nop \(mov r8, r8\)
0+110 <[^>]+> d010 beq.n 0+134 <[^>]+>
0+112 <[^>]+> d10f bne.n 0+134 <[^>]+>

6
gas/testsuite/gas/arm/thumb1_unified.d
View file

@ -7,9 +7,9 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> 200c movs r0, #12
0[0-9a-f]+ <[^>]+> 1cd1 adds r1, r2, #3
0[0-9a-f]+ <[^>]+> 1ed1 subs r1, r2, #3
0[0-9a-f]+ <[^>]+> 3364 adds r3, #100
0[0-9a-f]+ <[^>]+> 3c83 subs r4, #131
0[0-9a-f]+ <[^>]+> 2d27 cmp r5, #39
0[0-9a-f]+ <[^>]+> 3364 adds r3, #100.*
0[0-9a-f]+ <[^>]+> 3c83 subs r4, #131.*
0[0-9a-f]+ <[^>]+> 2d27 cmp r5, #39.*
0[0-9a-f]+ <[^>]+> a103 add r1, pc, #12 \(adr [^)]*\)
0[0-9a-f]+ <[^>]+> 4a03 ldr r2, \[pc, #12\] \([^)]*\)
0[0-9a-f]+ <[^>]+> 6863 ldr r3, \[r4, #4\]

6
gas/testsuite/gas/arm/thumb2_add.d
View file

@ -18,13 +18,13 @@ Disassembly of section .text:
0+02c <[^>]+> f2a1 1301 subw r3, r1, #257 ; 0x101
0+030 <[^>]+> f103 0301 add.w r3, r3, #1 ; 0x1
0+034 <[^>]+> f1a3 0301 sub.w r3, r3, #1 ; 0x1
0+038 <[^>]+> b0c0 sub sp, #256
0+038 <[^>]+> b0c0 sub sp, #256.*
0+03a <[^>]+> f5ad 7d00 sub.w sp, sp, #512 ; 0x200
0+03e <[^>]+> f2ad 1d01 subw sp, sp, #257 ; 0x101
0+042 <[^>]+> b040 add sp, #256
0+042 <[^>]+> b040 add sp, #256.*
0+044 <[^>]+> f50d 7d00 add.w sp, sp, #512 ; 0x200
0+048 <[^>]+> f20d 1d01 addw sp, sp, #257 ; 0x101
0+04c <[^>]+> a840 add r0, sp, #256
0+04c <[^>]+> a840 add r0, sp, #256.*
0+04e <[^>]+> f50d 6580 add.w r5, sp, #1024 ; 0x400
0+052 <[^>]+> f20d 1901 addw r9, sp, #257 ; 0x101
0+056 <[^>]+> 4271 negs r1, r6

86
gas/testsuite/gas/arm/thumb2_relax.d
View file

@ -5,7 +5,7 @@
Disassembly of section .text:
0+000 <[^>]+> 7829 ldrb r1, \[r5, #0\]
0+002 <[^>]+> f895 1023 ldrb.w r1, \[r5, #35\]
0+002 <[^>]+> f895 1023 ldrb.w r1, \[r5, #35\].*
0+006 <[^>]+> 7fe9 ldrb r1, \[r5, #31\]
0+008 <[^>]+> f895 101f ldrb.w r1, \[r5, #31\]
0+00c <[^>]+> f815 1c1f ldrb.w r1, \[r5, #-31\]
@ -23,7 +23,7 @@ Disassembly of section .text:
0+03a <[^>]+> bf00 nop
0+03c <[^>]+> bf00 nop
0+03e <[^>]+> f995 1000 ldrsb.w r1, \[r5\]
0+042 <[^>]+> f995 1023 ldrsb.w r1, \[r5, #35\]
0+042 <[^>]+> f995 1023 ldrsb.w r1, \[r5, #35\].*
0+046 <[^>]+> f995 101f ldrsb.w r1, \[r5, #31\]
0+04a <[^>]+> f995 101f ldrsb.w r1, \[r5, #31\]
0+04e <[^>]+> f915 1c1f ldrsb.w r1, \[r5, #-31\]
@ -40,14 +40,14 @@ Disassembly of section .text:
0+078 <[^>]+> f91f 103e ldrsb.w r1, \[pc, #-62\] ; 0+03e <[^>]+>
0+07c <[^>]+> bf00 nop
0+07e <[^>]+> 8829 ldrh r1, \[r5, #0\]
0+080 <[^>]+> f8b5 1042 ldrh.w r1, \[r5, #66\]
0+084 <[^>]+> 8fe9 ldrh r1, \[r5, #62\]
0+086 <[^>]+> f8b5 103e ldrh.w r1, \[r5, #62\]
0+08a <[^>]+> f835 1c3e ldrh.w r1, \[r5, #-62\]
0+08e <[^>]+> f835 1b3e ldrh.w r1, \[r5\], #62
0+092 <[^>]+> f835 1b3e ldrh.w r1, \[r5\], #62
0+096 <[^>]+> f835 1f3e ldrh.w r1, \[r5, #62\]!
0+09a <[^>]+> f835 1d3e ldrh.w r1, \[r5, #-62\]!
0+080 <[^>]+> f8b5 1042 ldrh.w r1, \[r5, #66\].*
0+084 <[^>]+> 8fe9 ldrh r1, \[r5, #62\].*
0+086 <[^>]+> f8b5 103e ldrh.w r1, \[r5, #62\].*
0+08a <[^>]+> f835 1c3e ldrh.w r1, \[r5, #-62\].*
0+08e <[^>]+> f835 1b3e ldrh.w r1, \[r5\], #62.*
0+092 <[^>]+> f835 1b3e ldrh.w r1, \[r5\], #62.*
0+096 <[^>]+> f835 1f3e ldrh.w r1, \[r5, #62\]!.*
0+09a <[^>]+> f835 1d3e ldrh.w r1, \[r5, #-62\]!.*
0+09e <[^>]+> 5b29 ldrh r1, \[r5, r4\]
0+0a0 <[^>]+> f839 100c ldrh.w r1, \[r9, ip\]
0+0a4 <[^>]+> f8bf 1010 ldrh.w r1, \[pc, #16\] ; 0+0b8 <[^>]+>
@ -57,14 +57,14 @@ Disassembly of section .text:
0+0b4 <[^>]+> f83f 103a ldrh.w r1, \[pc, #-58\] ; 0+07e <[^>]+>
0+0b8 <[^>]+> bf00 nop
0+0ba <[^>]+> f9b5 1000 ldrsh.w r1, \[r5\]
0+0be <[^>]+> f9b5 1042 ldrsh.w r1, \[r5, #66\]
0+0c2 <[^>]+> f9b5 103e ldrsh.w r1, \[r5, #62\]
0+0c6 <[^>]+> f9b5 103e ldrsh.w r1, \[r5, #62\]
0+0ca <[^>]+> f935 1c3e ldrsh.w r1, \[r5, #-62\]
0+0ce <[^>]+> f935 1b3e ldrsh.w r1, \[r5\], #62
0+0d2 <[^>]+> f935 1b3e ldrsh.w r1, \[r5\], #62
0+0d6 <[^>]+> f935 1f3e ldrsh.w r1, \[r5, #62\]!
0+0da <[^>]+> f935 1d3e ldrsh.w r1, \[r5, #-62\]!
0+0be <[^>]+> f9b5 1042 ldrsh.w r1, \[r5, #66\].*
0+0c2 <[^>]+> f9b5 103e ldrsh.w r1, \[r5, #62\].*
0+0c6 <[^>]+> f9b5 103e ldrsh.w r1, \[r5, #62\].*
0+0ca <[^>]+> f935 1c3e ldrsh.w r1, \[r5, #-62\].*
0+0ce <[^>]+> f935 1b3e ldrsh.w r1, \[r5\], #62.*
0+0d2 <[^>]+> f935 1b3e ldrsh.w r1, \[r5\], #62.*
0+0d6 <[^>]+> f935 1f3e ldrsh.w r1, \[r5, #62\]!.*
0+0da <[^>]+> f935 1d3e ldrsh.w r1, \[r5, #-62\]!.*
0+0de <[^>]+> 5f29 ldrsh r1, \[r5, r4\]
0+0e0 <[^>]+> f939 100c ldrsh.w r1, \[r9, ip\]
0+0e4 <[^>]+> f9bf 1010 ldrsh.w r1, \[pc, #16\] ; 0+0f8 <[^>]+>
@ -74,14 +74,14 @@ Disassembly of section .text:
0+0f4 <[^>]+> f93f 103e ldrsh.w r1, \[pc, #-62\] ; 0+0ba <[^>]+>
0+0f8 <[^>]+> bf00 nop
0+0fa <[^>]+> 6829 ldr r1, \[r5, #0\]
0+0fc <[^>]+> f8d5 1080 ldr.w r1, \[r5, #128\]
0+100 <[^>]+> 6fe9 ldr r1, \[r5, #124\]
0+102 <[^>]+> f8d5 107c ldr.w r1, \[r5, #124\]
0+106 <[^>]+> f855 1c7c ldr.w r1, \[r5, #-124\]
0+10a <[^>]+> f855 1b7c ldr.w r1, \[r5\], #124
0+10e <[^>]+> f855 1b7c ldr.w r1, \[r5\], #124
0+112 <[^>]+> f855 1f7c ldr.w r1, \[r5, #124\]!
0+116 <[^>]+> f855 1d7c ldr.w r1, \[r5, #-124\]!
0+0fc <[^>]+> f8d5 1080 ldr.w r1, \[r5, #128\].*
0+100 <[^>]+> 6fe9 ldr r1, \[r5, #124\].*
0+102 <[^>]+> f8d5 107c ldr.w r1, \[r5, #124\].*
0+106 <[^>]+> f855 1c7c ldr.w r1, \[r5, #-124\].*
0+10a <[^>]+> f855 1b7c ldr.w r1, \[r5\], #124.*
0+10e <[^>]+> f855 1b7c ldr.w r1, \[r5\], #124.*
0+112 <[^>]+> f855 1f7c ldr.w r1, \[r5, #124\]!.*
0+116 <[^>]+> f855 1d7c ldr.w r1, \[r5, #-124\]!.*
0+11a <[^>]+> 5929 ldr r1, \[r5, r4\]
0+11c <[^>]+> f859 100c ldr.w r1, \[r9, ip\]
0+120 <[^>]+> 4904 ldr r1, \[pc, #16\] \(0+134 <[^>]+>\)
@ -92,7 +92,7 @@ Disassembly of section .text:
0+132 <[^>]+> bf00 nop
0+134 <[^>]+> bf00 nop
0+136 <[^>]+> 7029 strb r1, \[r5, #0\]
0+138 <[^>]+> f885 1023 strb.w r1, \[r5, #35\]
0+138 <[^>]+> f885 1023 strb.w r1, \[r5, #35\].*
0+13c <[^>]+> 77e9 strb r1, \[r5, #31\]
0+13e <[^>]+> f885 101f strb.w r1, \[r5, #31\]
0+142 <[^>]+> f805 1c1f strb.w r1, \[r5, #-31\]
@ -109,14 +109,14 @@ Disassembly of section .text:
0+16c <[^>]+> f80f 103a strb.w r1, \[pc, #-58\] ; 0+136 <[^>]+>
0+170 <[^>]+> bf00 nop
0+172 <[^>]+> 8029 strh r1, \[r5, #0\]
0+174 <[^>]+> f8a5 1042 strh.w r1, \[r5, #66\]
0+178 <[^>]+> 87e9 strh r1, \[r5, #62\]
0+17a <[^>]+> f8a5 103e strh.w r1, \[r5, #62\]
0+17e <[^>]+> f825 1c3e strh.w r1, \[r5, #-62\]
0+182 <[^>]+> f825 1b3e strh.w r1, \[r5\], #62
0+186 <[^>]+> f825 1b3e strh.w r1, \[r5\], #62
0+18a <[^>]+> f825 1f3e strh.w r1, \[r5, #62\]!
0+18e <[^>]+> f825 1d3e strh.w r1, \[r5, #-62\]!
0+174 <[^>]+> f8a5 1042 strh.w r1, \[r5, #66\].*
0+178 <[^>]+> 87e9 strh r1, \[r5, #62\].*
0+17a <[^>]+> f8a5 103e strh.w r1, \[r5, #62\].*
0+17e <[^>]+> f825 1c3e strh.w r1, \[r5, #-62\].*
0+182 <[^>]+> f825 1b3e strh.w r1, \[r5\], #62.*
0+186 <[^>]+> f825 1b3e strh.w r1, \[r5\], #62.*
0+18a <[^>]+> f825 1f3e strh.w r1, \[r5, #62\]!.*
0+18e <[^>]+> f825 1d3e strh.w r1, \[r5, #-62\]!.*
0+192 <[^>]+> 5329 strh r1, \[r5, r4\]
0+194 <[^>]+> f829 100c strh.w r1, \[r9, ip\]
0+198 <[^>]+> f8af 1010 strh.w r1, \[pc, #16\] ; 0+1ac <[^>]+>
@ -126,14 +126,14 @@ Disassembly of section .text:
0+1a8 <[^>]+> f82f 103a strh.w r1, \[pc, #-58\] ; 0+172 <[^>]+>
0+1ac <[^>]+> bf00 nop
0+1ae <[^>]+> 6029 str r1, \[r5, #0\]
0+1b0 <[^>]+> f8c5 1080 str.w r1, \[r5, #128\]
0+1b4 <[^>]+> 67e9 str r1, \[r5, #124\]
0+1b6 <[^>]+> f8c5 107c str.w r1, \[r5, #124\]
0+1ba <[^>]+> f845 1c7c str.w r1, \[r5, #-124\]
0+1be <[^>]+> f845 1b7c str.w r1, \[r5\], #124
0+1c2 <[^>]+> f845 1b7c str.w r1, \[r5\], #124
0+1c6 <[^>]+> f845 1f7c str.w r1, \[r5, #124\]!
0+1ca <[^>]+> f845 1d7c str.w r1, \[r5, #-124\]!
0+1b0 <[^>]+> f8c5 1080 str.w r1, \[r5, #128\].*
0+1b4 <[^>]+> 67e9 str r1, \[r5, #124\].*
0+1b6 <[^>]+> f8c5 107c str.w r1, \[r5, #124\].*
0+1ba <[^>]+> f845 1c7c str.w r1, \[r5, #-124\].*
0+1be <[^>]+> f845 1b7c str.w r1, \[r5\], #124.*
0+1c2 <[^>]+> f845 1b7c str.w r1, \[r5\], #124.*
0+1c6 <[^>]+> f845 1f7c str.w r1, \[r5, #124\]!.*
0+1ca <[^>]+> f845 1d7c str.w r1, \[r5, #-124\]!.*
0+1ce <[^>]+> 5129 str r1, \[r5, r4\]
0+1d0 <[^>]+> f849 100c str.w r1, \[r9, ip\]
0+1d4 <[^>]+> f8cf 1010 str.w r1, \[pc, #16\] ; 0+1e8 <[^>]+>

120
gas/testsuite/gas/arm/thumb32.d
View file

@ -48,9 +48,9 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> 1c05 adds r5, r0, #0
0[0-9a-f]+ <[^>]+> 1c28 adds r0, r5, #0
0[0-9a-f]+ <[^>]+> 1d50 adds r0, r2, #5
0[0-9a-f]+ <[^>]+> 3081 adds r0, #129
0[0-9a-f]+ <[^>]+> 3081 adds r0, #129
0[0-9a-f]+ <[^>]+> 357e adds r5, #126
0[0-9a-f]+ <[^>]+> 3081 adds r0, #129.*
0[0-9a-f]+ <[^>]+> 3081 adds r0, #129.*
0[0-9a-f]+ <[^>]+> 357e adds r5, #126.*
0[0-9a-f]+ <[^>]+> 1800 adds r0, r0, r0
0[0-9a-f]+ <[^>]+> 1805 adds r5, r0, r0
0[0-9a-f]+ <[^>]+> 1828 adds r0, r5, r0
@ -68,10 +68,10 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 \(adr r0, [0-9a-f]+ <[^>]+>\)
0[0-9a-f]+ <[^>]+> a800 add r0, sp, #0
0[0-9a-f]+ <[^>]+> ad00 add r5, sp, #0
0[0-9a-f]+ <[^>]+> a881 add r0, sp, #516
0[0-9a-f]+ <[^>]+> a881 add r0, sp, #516.*
0[0-9a-f]+ <[^>]+> b000 add sp, #0
0[0-9a-f]+ <[^>]+> b000 add sp, #0
0[0-9a-f]+ <[^>]+> b041 add sp, #260
0[0-9a-f]+ <[^>]+> b041 add sp, #260.*
0[0-9a-f]+ <[^>]+> f100 0000 add\.w r0, r0, #0 ; 0x0
0[0-9a-f]+ <[^>]+> f110 0000 adds\.w r0, r0, #0 ; 0x0
0[0-9a-f]+ <[^>]+> f100 0900 add\.w r9, r0, #0 ; 0x0
@ -98,14 +98,14 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> 1e05 subs r5, r0, #0
0[0-9a-f]+ <[^>]+> 1e28 subs r0, r5, #0
0[0-9a-f]+ <[^>]+> 1f50 subs r0, r2, #5
0[0-9a-f]+ <[^>]+> 3881 subs r0, #129
0[0-9a-f]+ <[^>]+> 3881 subs r0, #129.*
0[0-9a-f]+ <[^>]+> 3d08 subs r5, #8
0[0-9a-f]+ <[^>]+> 1a00 subs r0, r0, r0
0[0-9a-f]+ <[^>]+> 1a05 subs r5, r0, r0
0[0-9a-f]+ <[^>]+> 1a28 subs r0, r5, r0
0[0-9a-f]+ <[^>]+> 1b40 subs r0, r0, r5
0[0-9a-f]+ <[^>]+> b0c1 sub sp, #260
0[0-9a-f]+ <[^>]+> b0c1 sub sp, #260
0[0-9a-f]+ <[^>]+> b0c1 sub sp, #260.*
0[0-9a-f]+ <[^>]+> b0c1 sub sp, #260.*
0[0-9a-f]+ <[^>]+> ebb8 0800 subs\.w r8, r8, r0
0[0-9a-f]+ <[^>]+> ebb0 0008 subs\.w r0, r0, r8
0[0-9a-f]+ <[^>]+> f5b0 7082 subs\.w r0, r0, #260 ; 0x104
@ -361,7 +361,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3af 8003 wfi\.w
0[0-9a-f]+ <[^>]+> f3af 8004 sev\.w
0[0-9a-f]+ <[^>]+> bf90 nop \{9\}
0[0-9a-f]+ <[^>]+> f3af 8081 nop\.w \{129\}
0[0-9a-f]+ <[^>]+> f3af 8081 nop\.w \{129\}.*
0[0-9a-f]+ <[^>]+> bf08 it eq
0[0-9a-f]+ <[^>]+> bf00 nopeq
0[0-9a-f]+ <[^>]+> bf18 it ne
@ -521,32 +521,32 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> bf00 nopeq
0[0-9a-f]+ <[^>]+> bf00 nopeq
0[0-9a-f]+ <[^>]+> f895 f000 pld \[r5\]
0[0-9a-f]+ <[^>]+> f895 f330 pld \[r5, #816\]
0[0-9a-f]+ <[^>]+> f815 fc30 pld \[r5, #-48\]
0[0-9a-f]+ <[^>]+> f815 fb30 pld \[r5\], #48
0[0-9a-f]+ <[^>]+> f815 f930 pld \[r5\], #-48
0[0-9a-f]+ <[^>]+> f815 ff30 pld \[r5, #48\]!
0[0-9a-f]+ <[^>]+> f815 fd30 pld \[r5, #-48\]!
0[0-9a-f]+ <[^>]+> f895 f330 pld \[r5, #816\].*
0[0-9a-f]+ <[^>]+> f815 fc30 pld \[r5, #-48\].*
0[0-9a-f]+ <[^>]+> f815 fb30 pld \[r5\], #48.*
0[0-9a-f]+ <[^>]+> f815 f930 pld \[r5\], #-48.*
0[0-9a-f]+ <[^>]+> f815 ff30 pld \[r5, #48\]!.*
0[0-9a-f]+ <[^>]+> f815 fd30 pld \[r5, #-48\]!.*
0[0-9a-f]+ <[^>]+> f815 f004 pld \[r5, r4\]
0[0-9a-f]+ <[^>]+> f819 f00c pld \[r9, ip\]
0[0-9a-f]+ <[^>]+> f89f f006 pld \[pc, #6\] ; 0+5ee <[^>]+>
0[0-9a-f]+ <[^>]+> f81f f02a pld \[pc, #-42\] ; 0+5c2 <[^>]+>
0[0-9a-f]+ <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\]
0[0-9a-f]+ <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\]
0[0-9a-f]+ <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\]
0[0-9a-f]+ <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\].*
0[0-9a-f]+ <[^>]+> e9c5 2300 strd r2, r3, \[r5\]
0[0-9a-f]+ <[^>]+> e9c5 230c strd r2, r3, \[r5, #48\]
0[0-9a-f]+ <[^>]+> e945 230c strd r2, r3, \[r5, #-48\]
0[0-9a-f]+ <[^>]+> e9c5 230c strd r2, r3, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> e945 230c strd r2, r3, \[r5, #-48\].*
0[0-9a-f]+ <[^>]+> f815 1e00 ldrbt r1, \[r5\]
0[0-9a-f]+ <[^>]+> f815 1e30 ldrbt r1, \[r5, #48\]
0[0-9a-f]+ <[^>]+> f815 1e30 ldrbt r1, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> f915 1e00 ldrsbt r1, \[r5\]
0[0-9a-f]+ <[^>]+> f915 1e30 ldrsbt r1, \[r5, #48\]
0[0-9a-f]+ <[^>]+> f915 1e30 ldrsbt r1, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> f835 1e00 ldrht r1, \[r5\]
0[0-9a-f]+ <[^>]+> f835 1e30 ldrht r1, \[r5, #48\]
0[0-9a-f]+ <[^>]+> f835 1e30 ldrht r1, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> f935 1e00 ldrsht r1, \[r5\]
0[0-9a-f]+ <[^>]+> f935 1e30 ldrsht r1, \[r5, #48\]
0[0-9a-f]+ <[^>]+> f935 1e30 ldrsht r1, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> f855 1e00 ldrt r1, \[r5\]
0[0-9a-f]+ <[^>]+> f855 1e30 ldrt r1, \[r5, #48\]
0[0-9a-f]+ <[^>]+> f855 1e30 ldrt r1, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> e8d4 1f4f ldrexb r1, \[r4\]
0[0-9a-f]+ <[^>]+> e8d4 1f5f ldrexh r1, \[r4\]
0[0-9a-f]+ <[^>]+> e854 1f00 ldrex r1, \[r4\]
@ -555,8 +555,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e8c4 2f51 strexh r1, r2, \[r4\]
0[0-9a-f]+ <[^>]+> e844 2100 strex r1, r2, \[r4\]
0[0-9a-f]+ <[^>]+> e8c4 2371 strexd r1, r2, r3, \[r4\]
0[0-9a-f]+ <[^>]+> e854 1f81 ldrex r1, \[r4, #516\]
0[0-9a-f]+ <[^>]+> e844 2181 strex r1, r2, \[r4, #516\]
0[0-9a-f]+ <[^>]+> e854 1f81 ldrex r1, \[r4, #516\].*
0[0-9a-f]+ <[^>]+> e844 2181 strex r1, r2, \[r4, #516\].*
0[0-9a-f]+ <[^>]+> c80e ldmia r0!, \{r1, r2, r3\}
0[0-9a-f]+ <[^>]+> ca07 ldmia r2!, \{r0, r1, r2\}
0[0-9a-f]+ <[^>]+> e892 0007 ldmia\.w r2, \{r0, r1, r2\}
@ -993,44 +993,44 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0
0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0
0[0-9a-f]+ <[^>]+> f3de 8f04 subs pc, lr, #4
0[0-9a-f]+ <[^>]+> f3de 8fff subs pc, lr, #255
0[0-9a-f]+ <[^>]+> e9f9 240c ldrd r2, r4, \[r9, #48\]!
0[0-9a-f]+ <[^>]+> e979 240c ldrd r2, r4, \[r9, #-48\]!
0[0-9a-f]+ <[^>]+> e9e9 240c strd r2, r4, \[r9, #48\]!
0[0-9a-f]+ <[^>]+> e969 240c strd r2, r4, \[r9, #-48\]!
0[0-9a-f]+ <[^>]+> e8f9 240c ldrd r2, r4, \[r9\], #48
0[0-9a-f]+ <[^>]+> e879 240c ldrd r2, r4, \[r9\], #-48
0[0-9a-f]+ <[^>]+> e8e9 240c strd r2, r4, \[r9\], #48
0[0-9a-f]+ <[^>]+> e869 240c strd r2, r4, \[r9\], #-48
0[0-9a-f]+ <[^>]+> f8d5 1301 ldr.w r1, \[r5, #769]
0[0-9a-f]+ <[^>]+> f855 1f30 ldr.w r1, \[r5, #48]!
0[0-9a-f]+ <[^>]+> f855 1d30 ldr.w r1, \[r5, #-48]!
0[0-9a-f]+ <[^>]+> f855 1b30 ldr.w r1, \[r5\], #48
0[0-9a-f]+ <[^>]+> f855 1930 ldr.w r1, \[r5\], #-48
0[0-9a-f]+ <[^>]+> f3de 8fff subs pc, lr, #255.*
0[0-9a-f]+ <[^>]+> e9f9 240c ldrd r2, r4, \[r9, #48\]!.*
0[0-9a-f]+ <[^>]+> e979 240c ldrd r2, r4, \[r9, #-48\]!.*
0[0-9a-f]+ <[^>]+> e9e9 240c strd r2, r4, \[r9, #48\]!.*
0[0-9a-f]+ <[^>]+> e969 240c strd r2, r4, \[r9, #-48\]!.*
0[0-9a-f]+ <[^>]+> e8f9 240c ldrd r2, r4, \[r9\], #48.*
0[0-9a-f]+ <[^>]+> e879 240c ldrd r2, r4, \[r9\], #-48.*
0[0-9a-f]+ <[^>]+> e8e9 240c strd r2, r4, \[r9\], #48.*
0[0-9a-f]+ <[^>]+> e869 240c strd r2, r4, \[r9\], #-48.*
0[0-9a-f]+ <[^>]+> f8d5 1301 ldr.w r1, \[r5, #769].*
0[0-9a-f]+ <[^>]+> f855 1f30 ldr.w r1, \[r5, #48]!.*
0[0-9a-f]+ <[^>]+> f855 1d30 ldr.w r1, \[r5, #-48]!.*
0[0-9a-f]+ <[^>]+> f855 1b30 ldr.w r1, \[r5\], #48.*
0[0-9a-f]+ <[^>]+> f855 1930 ldr.w r1, \[r5\], #-48.*
0[0-9a-f]+ <[^>]+> f855 1009 ldr.w r1, \[r5, r9\]
0[0-9a-f]+ <[^>]+> f895 1301 ldrb.w r1, \[r5, #769]
0[0-9a-f]+ <[^>]+> f815 1f30 ldrb.w r1, \[r5, #48]!
0[0-9a-f]+ <[^>]+> f815 1d30 ldrb.w r1, \[r5, #-48]!
0[0-9a-f]+ <[^>]+> f815 1b30 ldrb.w r1, \[r5\], #48
0[0-9a-f]+ <[^>]+> f815 1930 ldrb.w r1, \[r5\], #-48
0[0-9a-f]+ <[^>]+> f895 1301 ldrb.w r1, \[r5, #769].*
0[0-9a-f]+ <[^>]+> f815 1f30 ldrb.w r1, \[r5, #48]!.*
0[0-9a-f]+ <[^>]+> f815 1d30 ldrb.w r1, \[r5, #-48]!.*
0[0-9a-f]+ <[^>]+> f815 1b30 ldrb.w r1, \[r5\], #48.*
0[0-9a-f]+ <[^>]+> f815 1930 ldrb.w r1, \[r5\], #-48.*
0[0-9a-f]+ <[^>]+> f815 1009 ldrb.w r1, \[r5, r9\]
0[0-9a-f]+ <[^>]+> f995 1301 ldrsb.w r1, \[r5, #769]
0[0-9a-f]+ <[^>]+> f915 1f30 ldrsb.w r1, \[r5, #48]!
0[0-9a-f]+ <[^>]+> f915 1d30 ldrsb.w r1, \[r5, #-48]!
0[0-9a-f]+ <[^>]+> f915 1b30 ldrsb.w r1, \[r5\], #48
0[0-9a-f]+ <[^>]+> f915 1930 ldrsb.w r1, \[r5\], #-48
0[0-9a-f]+ <[^>]+> f995 1301 ldrsb.w r1, \[r5, #769].*
0[0-9a-f]+ <[^>]+> f915 1f30 ldrsb.w r1, \[r5, #48]!.*
0[0-9a-f]+ <[^>]+> f915 1d30 ldrsb.w r1, \[r5, #-48]!.*
0[0-9a-f]+ <[^>]+> f915 1b30 ldrsb.w r1, \[r5\], #48.*
0[0-9a-f]+ <[^>]+> f915 1930 ldrsb.w r1, \[r5\], #-48.*
0[0-9a-f]+ <[^>]+> f915 1009 ldrsb.w r1, \[r5, r9\]
0[0-9a-f]+ <[^>]+> f8b5 1301 ldrh.w r1, \[r5, #769]
0[0-9a-f]+ <[^>]+> f835 1f30 ldrh.w r1, \[r5, #48]!
0[0-9a-f]+ <[^>]+> f835 1d30 ldrh.w r1, \[r5, #-48]!
0[0-9a-f]+ <[^>]+> f835 1b30 ldrh.w r1, \[r5\], #48
0[0-9a-f]+ <[^>]+> f835 1930 ldrh.w r1, \[r5\], #-48
0[0-9a-f]+ <[^>]+> f8b5 1301 ldrh.w r1, \[r5, #769].*
0[0-9a-f]+ <[^>]+> f835 1f30 ldrh.w r1, \[r5, #48]!.*
0[0-9a-f]+ <[^>]+> f835 1d30 ldrh.w r1, \[r5, #-48]!.*
0[0-9a-f]+ <[^>]+> f835 1b30 ldrh.w r1, \[r5\], #48.*
0[0-9a-f]+ <[^>]+> f835 1930 ldrh.w r1, \[r5\], #-48.*
0[0-9a-f]+ <[^>]+> f835 1009 ldrh.w r1, \[r5, r9\]
0[0-9a-f]+ <[^>]+> f9b5 1301 ldrsh.w r1, \[r5, #769]
0[0-9a-f]+ <[^>]+> f935 1f30 ldrsh.w r1, \[r5, #48]!
0[0-9a-f]+ <[^>]+> f935 1d30 ldrsh.w r1, \[r5, #-48]!
0[0-9a-f]+ <[^>]+> f935 1b30 ldrsh.w r1, \[r5\], #48
0[0-9a-f]+ <[^>]+> f935 1930 ldrsh.w r1, \[r5\], #-48
0[0-9a-f]+ <[^>]+> f9b5 1301 ldrsh.w r1, \[r5, #769].*
0[0-9a-f]+ <[^>]+> f935 1f30 ldrsh.w r1, \[r5, #48]!.*
0[0-9a-f]+ <[^>]+> f935 1d30 ldrsh.w r1, \[r5, #-48]!.*
0[0-9a-f]+ <[^>]+> f935 1b30 ldrsh.w r1, \[r5\], #48.*
0[0-9a-f]+ <[^>]+> f935 1930 ldrsh.w r1, \[r5\], #-48.*
0[0-9a-f]+ <[^>]+> f935 1009 ldrsh.w r1, \[r5, r9\]
0[0-9a-f]+ <[^>]+> 00a1 lsls r1, r4, #2
0[0-9a-f]+ <[^>]+> ea5f 0389 movs.w r3, r9, lsl #2

8
gas/testsuite/gas/arm/vfp-neon-syntax.d
View file

@ -7,16 +7,16 @@
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> eeb00a60 (vmov\.f32|fcpys) s0, s1
0[0-9a-f]+ <[^>]+> eeb00b41 (vmov\.f64|fcpyd) d0, d1
0[0-9a-f]+ <[^>]+> eeb50a00 (vmov\.f32|fconsts) s0, #80
0[0-9a-f]+ <[^>]+> eeb70b00 (vmov\.f64|fconstd) d0, #112
0[0-9a-f]+ <[^>]+> eeb50a00 (vmov\.f32|fconsts) s0, #80.*
0[0-9a-f]+ <[^>]+> eeb70b00 (vmov\.f64|fconstd) d0, #112.*
0[0-9a-f]+ <[^>]+> ee100a90 (vmov|fmrs) r0, s1
0[0-9a-f]+ <[^>]+> ee001a10 (vmov|fmsr) s0, r1
0[0-9a-f]+ <[^>]+> ec510a11 (vmov r0, r1, s2, s3|fmrrs r0, r1, {s2, s3})
0[0-9a-f]+ <[^>]+> ec442a10 (vmov s0, s1, r2, r4|fmsrr {s0, s1}, r2, r4)
0[0-9a-f]+ <[^>]+> 0eb00a60 (vmoveq\.f32|fcpyseq) s0, s1
0[0-9a-f]+ <[^>]+> 0eb00b41 (vmoveq\.f64|fcpydeq) d0, d1
0[0-9a-f]+ <[^>]+> 0eb50a00 (vmoveq\.f32|fconstseq) s0, #80
0[0-9a-f]+ <[^>]+> 0eb70b00 (vmoveq\.f64|fconstdeq) d0, #112
0[0-9a-f]+ <[^>]+> 0eb50a00 (vmoveq\.f32|fconstseq) s0, #80.*
0[0-9a-f]+ <[^>]+> 0eb70b00 (vmoveq\.f64|fconstdeq) d0, #112.*
0[0-9a-f]+ <[^>]+> 0e100a90 (vmoveq|fmrseq) r0, s1
0[0-9a-f]+ <[^>]+> 0e001a10 (vmoveq|fmsreq) s0, r1
0[0-9a-f]+ <[^>]+> 0c510a11 (vmoveq r0, r1, s2, s3|fmrrseq r0, r1, {s2, s3})

8
gas/testsuite/gas/arm/vfp-neon-syntax_t2.d
View file

@ -7,8 +7,8 @@
Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> eeb0 0a60 (vmov\.f32|fcpys) s0, s1
0[0-9a-f]+ <[^>]+> eeb0 0b41 (vmov\.f64|fcpyd) d0, d1
0[0-9a-f]+ <[^>]+> eeb5 0a00 (vmov\.f32|fconsts) s0, #80
0[0-9a-f]+ <[^>]+> eeb7 0b00 (vmov\.f64|fconstd) d0, #112
0[0-9a-f]+ <[^>]+> eeb5 0a00 (vmov\.f32|fconsts) s0, #80.*
0[0-9a-f]+ <[^>]+> eeb7 0b00 (vmov\.f64|fconstd) d0, #112.*
0[0-9a-f]+ <[^>]+> ee10 0a90 (vmov|fmrs) r0, s1
0[0-9a-f]+ <[^>]+> ee00 1a10 (vmov|fmsr) s0, r1
0[0-9a-f]+ <[^>]+> ec51 0a11 (vmov r0, r1, s2, s3|fmrrs r0, r1, {s2, s3})
@ -16,8 +16,8 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> bf01 itttt eq
0[0-9a-f]+ <[^>]+> eeb0 0a60 (vmoveq\.f32|fcpyseq) s0, s1
0[0-9a-f]+ <[^>]+> eeb0 0b41 (vmoveq\.f64|fcpydeq) d0, d1
0[0-9a-f]+ <[^>]+> eeb5 0a00 (vmoveq\.f32|fconstseq) s0, #80
0[0-9a-f]+ <[^>]+> eeb7 0b00 (vmoveq\.f64|fconstdeq) d0, #112
0[0-9a-f]+ <[^>]+> eeb5 0a00 (vmoveq\.f32|fconstseq) s0, #80.*
0[0-9a-f]+ <[^>]+> eeb7 0b00 (vmoveq\.f64|fconstdeq) d0, #112.*
0[0-9a-f]+ <[^>]+> bf01 itttt eq
0[0-9a-f]+ <[^>]+> ee10 0a90 (vmoveq|fmrseq) r0, s1
0[0-9a-f]+ <[^>]+> ee00 1a10 (vmoveq|fmsreq) s0, r1

6
gas/testsuite/gas/arm/vfp1xD.d
View file

@ -125,12 +125,12 @@ Disassembly of section .text:
0+1cc <[^>]*> ed910a00 (vldr|flds) s0, \[r1\]
0+1d0 <[^>]*> ed9e0a00 (vldr|flds) s0, \[lr\]
0+1d4 <[^>]*> ed900a00 (vldr|flds) s0, \[r0\]
0+1d8 <[^>]*> ed900aff (vldr|flds) s0, \[r0, #1020\]
0+1dc <[^>]*> ed100aff (vldr|flds) s0, \[r0, #-1020\]
0+1d8 <[^>]*> ed900aff (vldr|flds) s0, \[r0, #1020\].*
0+1dc <[^>]*> ed100aff (vldr|flds) s0, \[r0, #-1020\].*
0+1e0 <[^>]*> edd00a00 (vldr|flds) s1, \[r0\]
0+1e4 <[^>]*> ed901a00 (vldr|flds) s2, \[r0\]
0+1e8 <[^>]*> edd0fa00 (vldr|flds) s31, \[r0\]
0+1ec <[^>]*> edccaac9 (vstr|fsts) s21, \[ip, #804\]
0+1ec <[^>]*> edccaac9 (vstr|fsts) s21, \[ip, #804\].*
0+1f0 <[^>]*> ecd00a01 (vldmia|fldmias) r0, {s1}
0+1f4 <[^>]*> ec901a01 (vldmia|fldmias) r0, {s2}
0+1f8 <[^>]*> ecd0fa01 (vldmia|fldmias) r0, {s31}

6
gas/testsuite/gas/arm/vfp1xD_t2.d
View file

@ -125,12 +125,12 @@ Disassembly of section .text:
0+1cc <[^>]*> ed91 0a00 (vldr|flds) s0, \[r1\]
0+1d0 <[^>]*> ed9e 0a00 (vldr|flds) s0, \[lr\]
0+1d4 <[^>]*> ed90 0a00 (vldr|flds) s0, \[r0\]
0+1d8 <[^>]*> ed90 0aff (vldr|flds) s0, \[r0, #1020\]
0+1dc <[^>]*> ed10 0aff (vldr|flds) s0, \[r0, #-1020\]
0+1d8 <[^>]*> ed90 0aff (vldr|flds) s0, \[r0, #1020\].*
0+1dc <[^>]*> ed10 0aff (vldr|flds) s0, \[r0, #-1020\].*
0+1e0 <[^>]*> edd0 0a00 (vldr|flds) s1, \[r0\]
0+1e4 <[^>]*> ed90 1a00 (vldr|flds) s2, \[r0\]
0+1e8 <[^>]*> edd0 fa00 (vldr|flds) s31, \[r0\]
0+1ec <[^>]*> edcc aac9 (vstr|fsts) s21, \[ip, #804\]
0+1ec <[^>]*> edcc aac9 (vstr|fsts) s21, \[ip, #804\].*
0+1f0 <[^>]*> ecd0 0a01 (vldmia|fldmias) r0, {s1}
0+1f4 <[^>]*> ec90 1a01 (vldmia|fldmias) r0, {s2}
0+1f8 <[^>]*> ecd0 fa01 (vldmia|fldmias) r0, {s31}

8
gas/testsuite/gas/arm/vfpv3-const-conv.d
View file

@ -6,11 +6,11 @@
Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> eef08a04 (vmov\.f32|fconsts) s17, #4
0[0-9a-f]+ <[^>]+> eeba9a05 (vmov\.f32|fconsts) s18, #165
0[0-9a-f]+ <[^>]+> eef49a00 (vmov\.f32|fconsts) s19, #64
0[0-9a-f]+ <[^>]+> eeba9a05 (vmov\.f32|fconsts) s18, #165.*
0[0-9a-f]+ <[^>]+> eef49a00 (vmov\.f32|fconsts) s19, #64.*
0[0-9a-f]+ <[^>]+> eef01b04 (vmov\.f64|fconstd) d17, #4
0[0-9a-f]+ <[^>]+> eefa2b05 (vmov\.f64|fconstd) d18, #165
0[0-9a-f]+ <[^>]+> eef43b00 (vmov\.f64|fconstd) d19, #64
0[0-9a-f]+ <[^>]+> eefa2b05 (vmov\.f64|fconstd) d18, #165.*
0[0-9a-f]+ <[^>]+> eef43b00 (vmov\.f64|fconstd) d19, #64.*
0[0-9a-f]+ <[^>]+> eefa8a63 (vcvt\.f32\.s16 s17, s17, #9|fshtos s17, #9)
0[0-9a-f]+ <[^>]+> eefa1b63 (vcvt\.f64\.s16 d17, d17, #9|fshtod d17, #9)
0[0-9a-f]+ <[^>]+> eefa8aeb (vcvt\.f32\.s32 s17, s17, #9|fsltos s17, #9)

2
gas/testsuite/gas/arm/xscale.d
View file

@ -20,7 +20,7 @@ Disassembly of section .text:
0+28 <[^>]*> ec543000 mra r3, r4, acc0
0+2c <[^>]*> ec585000 mra r5, r8, acc0
0+30 <[^>]*> f5d0f000 pld \[r0\]
0+34 <[^>]*> f5d1f789 pld \[r1, #1929\]
0+34 <[^>]*> f5d1f789 pld \[r1, #1929\].*
0+38 <[^>]*> f7d2f003 pld \[r2, r3\]
0+3c <[^>]*> f754f285 pld \[r4, -r5, lsl #5\]
0+40 <[^>]*> e1c100d0 ldrd r0, \[r1\]

18
ld/testsuite/ChangeLog
View file

@ -1,3 +1,21 @@
2009-06-29 Nick Clifton <nickc@redhat.com>
PR 10288
* ld-arm/arm-app-abs32.d: Update expected disassembly.
* ld-arm/arm-app.d: Likewise.
* ld-arm/arm-lib-plt32.d: Likewise.
* ld-arm/arm-lib.d: Likewise.
* ld-arm/arm-pic-veneer.d: Likewise.
* ld-arm/armthumb-lib.d: Likewise.
* ld-arm/farcall-mixed-app-v5.d: Likewise.
* ld-arm/farcall-mixed-app.d: Likewise.
* ld-arm/farcall-mixed-lib.d: Likewise.
* ld-arm/group-relocs.d: Likewise.
* ld-arm/mixed-app-v5.d: Likewise.
* ld-arm/mixed-app.d: Likewise.
* ld-arm/mixed-lib.d: Likewise.
* ld-arm/thumb2-bl-undefweak.d: Likewise.
2009-06-27 H.J. Lu <hongjiu.lu@intel.com>
PR ld/10337

2
ld/testsuite/ld-arm/arm-app-abs32.d
View file

@ -14,7 +14,7 @@ Disassembly of section .plt:
.*: .* .*
.*: e28fc6.* add ip, pc, #.* ; .*
.*: e28cca.* add ip, ip, #.* ; .*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <_start>:

2
ld/testsuite/ld-arm/arm-app.d
View file

@ -14,7 +14,7 @@ Disassembly of section .plt:
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <_start>:

2
ld/testsuite/ld-arm/arm-lib-plt32.d
View file

@ -14,7 +14,7 @@ Disassembly of section .plt:
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <lib_func1>:

2
ld/testsuite/ld-arm/arm-lib.d
View file

@ -14,7 +14,7 @@ Disassembly of section .plt:
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <lib_func1>:

2
ld/testsuite/ld-arm/arm-pic-veneer.d
View file

@ -4,7 +4,7 @@
Disassembly of section .text:
00008000 <_start>:
8000: ea000000 b 8008 <__foo_from_arm>
8000: ea...... b 800. <.*>
00008004 <foo>:
8004: 46c0 nop \(mov r8, r8\)

2
ld/testsuite/ld-arm/armthumb-lib.d
View file

@ -14,7 +14,7 @@ Disassembly of section .plt:
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <lib_func1>:

4
ld/testsuite/ld-arm/farcall-mixed-app-v5.d
View file

@ -14,10 +14,10 @@ Disassembly of section .plt:
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:

4
ld/testsuite/ld-arm/farcall-mixed-app.d
View file

@ -16,10 +16,10 @@ Disassembly of section .plt:
.*: 46c0 nop \(mov r8, r8\)
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:

8
ld/testsuite/ld-arm/farcall-mixed-lib.d
View file

@ -13,16 +13,16 @@ Disassembly of section .plt:
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:

28
ld/testsuite/ld-arm/group-relocs.d
View file

@ -17,40 +17,40 @@ Disassembly of section .text:
8028: e2800cee add r0, r0, #60928 ; 0xee00
802c: e28000f0 add r0, r0, #240 ; 0xf0
8030: e2800c6e add r0, r0, #28160 ; 0x6e00
8034: e59010c0 ldr r1, \[r0, #192\]
8034: e59010c0 ldr r1, \[r0, #192\].*
8038: e28008ff add r0, r0, #16711680 ; 0xff0000
803c: e2800c6e add r0, r0, #28160 ; 0x6e00
8040: e59010b8 ldr r1, \[r0, #184\]
8040: e59010b8 ldr r1, \[r0, #184\].*
8044: e5901000 ldr r1, \[r0\]
8048: e2800cee add r0, r0, #60928 ; 0xee00
804c: e59010f0 ldr r1, \[r0, #240\]
804c: e59010f0 ldr r1, \[r0, #240\].*
8050: e28008ff add r0, r0, #16711680 ; 0xff0000
8054: e2800cee add r0, r0, #60928 ; 0xee00
8058: e59010f0 ldr r1, \[r0, #240\]
805c: e1c026d0 ldrd r2, \[r0, #96\]
8058: e59010f0 ldr r1, \[r0, #240\].*
805c: e1c026d0 ldrd r2, \[r0, #96\].*
8060: e2800c6e add r0, r0, #28160 ; 0x6e00
8064: e1c029d0 ldrd r2, \[r0, #144\]
8064: e1c029d0 ldrd r2, \[r0, #144\].*
8068: e28008ff add r0, r0, #16711680 ; 0xff0000
806c: e2800c6e add r0, r0, #28160 ; 0x6e00
8070: e1c028d8 ldrd r2, \[r0, #136\]
8070: e1c028d8 ldrd r2, \[r0, #136\].*
8074: e1c020d0 ldrd r2, \[r0\]
8078: e2800cee add r0, r0, #60928 ; 0xee00
807c: e1c02fd0 ldrd r2, \[r0, #240\]
807c: e1c02fd0 ldrd r2, \[r0, #240\].*
8080: e28008ff add r0, r0, #16711680 ; 0xff0000
8084: e2800cee add r0, r0, #60928 ; 0xee00
8088: e1c02fd0 ldrd r2, \[r0, #240\]
808c: ed90000c ldc 0, cr0, \[r0, #48\]
8088: e1c02fd0 ldrd r2, \[r0, #240\].*
808c: ed90000c ldc 0, cr0, \[r0, #48\].*
8090: e2800c6e add r0, r0, #28160 ; 0x6e00
8094: ed900018 ldc 0, cr0, \[r0, #96\]
8094: ed900018 ldc 0, cr0, \[r0, #96\].*
8098: e28008ff add r0, r0, #16711680 ; 0xff0000
809c: e2800c6e add r0, r0, #28160 ; 0x6e00
80a0: ed900016 ldc 0, cr0, \[r0, #88\]
80a0: ed900016 ldc 0, cr0, \[r0, #88\].*
80a4: ed900000 ldc 0, cr0, \[r0\]
80a8: e2800cee add r0, r0, #60928 ; 0xee00
80ac: ed90003c ldc 0, cr0, \[r0, #240\]
80ac: ed90003c ldc 0, cr0, \[r0, #240\].*
80b0: e28008ff add r0, r0, #16711680 ; 0xff0000
80b4: e2800cee add r0, r0, #60928 ; 0xee00
80b8: ed90003c ldc 0, cr0, \[r0, #240\]
80b8: ed90003c ldc 0, cr0, \[r0, #240\].*
000080bc <one_group_needed_alu_pc>:
80bc: e3a00000 mov r0, #0 ; 0x0

4
ld/testsuite/ld-arm/mixed-app-v5.d
View file

@ -14,10 +14,10 @@ Disassembly of section .plt:
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <_start>:

4
ld/testsuite/ld-arm/mixed-app.d
View file

@ -16,10 +16,10 @@ Disassembly of section .plt:
.*: 46c0 nop \(mov r8, r8\)
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <_start>:

2
ld/testsuite/ld-arm/mixed-lib.d
View file

@ -14,7 +14,7 @@ Disassembly of section .plt:
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <lib_func1>:

2
ld/testsuite/ld-arm/thumb2-bl-undefweak.d
View file

@ -6,4 +6,4 @@
Disassembly of section .text:
.* <foo>:
.*: .... .... blx ... <foo-0x.*>
.*: .... .... bl. ... <foo-0x.*>

26
opcodes/ChangeLog
View file

@ -1,3 +1,29 @@
2009-06-29 Nick Clifton <nickc@redhat.com>
PR 10288
* arm-dis.c (enum opcode_sentinels): New: Used to mark the
boundary between variaant and generic coprocessor instuctions.
(coprocessor): Use it.
Fix architecture version of MCRR and MRRC instructions.
(arm_opcdes): Fix patterns for STRB and STRH instructions.
(print_insn_coprocessor): Check architecture and extension masks.
Print a hexadecimal version of any decimal constant that is
outside of the range of -16 to +32.
(print_arm_address): Add a return value of the offset used in the
adress, if it is worth printing a hexadecimal version of it.
(print_insn_neon): Print a hexadecimal version of any decimal
constant that is outside of the range of -16 to +32.
(print_insn_arm): Likewise.
(print_insn_thumb16): Likewise.
(print_insn_thumb32): Likewise.
PR 10297
* arm-dis.c (UNDEFINED_INSTRUCTION): New macro for a description
of an undefined instruction.
(arm_opcodes): Use it.
(thumb_opcod): Use it.
(thumb32_opc): Use it.
2009-06-23 DJ Delorie <dj@redhat.com>
* mep-desc.c: Regenerate.

314
opcodes/arm-dis.c
View file

@ -48,8 +48,9 @@
struct opcode32
{
unsigned long arch; /* Architecture defining this insn. */
unsigned long value, mask; /* Recognise insn if (op&mask)==value. */
const char *assembler; /* How to disassemble this insn. */
unsigned long value; /* Recognise insn if (op & mask) == value. */
unsigned long mask; /* If arch == 0 then value is a sentinel. */
const char * assembler; /* How to disassemble this insn. */
};
struct opcode16
@ -106,6 +107,15 @@ struct opcode16
%r print register offset address for wldt/wstr instruction
*/
enum
{
SENTINEL_IWMMXT_START = 1,
SENTINEL_IWMMXT_END,
SENTINEL_GENERIC_START
} opcode_sentinels;
#define UNDEFINED_INSTRUCTION "undefined instruction %0-31x"
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
static const struct opcode32 coprocessor_opcodes[] =
@ -118,8 +128,7 @@ static const struct opcode32 coprocessor_opcodes[] =
{ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
/* Intel Wireless MMX technology instructions. */
#define FIRST_IWMMXT_INSN 0x0e130130
#define IWMMXT_INSN_COUNT 73
{ 0, SENTINEL_IWMMXT_START, 0, "" },
{ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
{ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
{ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
@ -195,6 +204,7 @@ static const struct opcode32 coprocessor_opcodes[] =
{ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
{ 0, SENTINEL_IWMMXT_END, 0, "" },
/* Floating point coprocessor (FPA) instructions */
{FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
@ -438,20 +448,21 @@ static const struct opcode32 coprocessor_opcodes[] =
{ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
/* Generic coprocessor instructions */
{ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
{ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
/* Generic coprocessor instructions. */
{ 0, SENTINEL_GENERIC_START, 0, "" },
{ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
{ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
{ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
{ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
/* V6 coprocessor instructions */
/* V6 coprocessor instructions. */
{ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
{ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
/* V5 coprocessor instructions */
/* V5 coprocessor instructions. */
{ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
{ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
{ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
@ -989,7 +1000,12 @@ static const struct opcode32 arm_opcodes[] =
{ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
/* ARM Instructions. */
{ARM_EXT_V1, 0x00000090, 0x0e100090, "str%6's%5?hb%c\t%12-15r, %s"},
{ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
{ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x04400000, 0x0c500000, "strb%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x000000b0, 0x0e1000f0, "strh%c\t%12-15r, %s"},
{ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%6's%5?hb%c\t%12-15r, %s"},
{ARM_EXT_V1, 0x00000000, 0x0de00000, "and%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
@ -1015,11 +1031,7 @@ static const struct opcode32 arm_opcodes[] =
{ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15r, %q"},
{ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
{ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%20's%c\t%12-15r, %o"},
{ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
{ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"},
{ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
{ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
{ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"},
{ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
@ -1032,7 +1044,7 @@ static const struct opcode32 arm_opcodes[] =
{ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
/* The rest. */
{ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"},
{ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
{0, 0x00000000, 0x00000000, 0}
};
@ -1169,7 +1181,7 @@ static const struct opcode16 thumb_opcodes[] =
/* format 17 */
{ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
/* format 16 */
{ARM_EXT_V4T, 0xDE00, 0xFE00, "undefined"},
{ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
{ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
/* format 18 */
{ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
@ -1178,7 +1190,7 @@ static const struct opcode16 thumb_opcodes[] =
32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
are processed via that table. Thus, we can never encounter a
bare "second half of BL/BLX(1)" instruction here. */
{ARM_EXT_V1, 0x0000, 0x0000, "undefined"},
{ARM_EXT_V1, 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
{0, 0, 0, 0}
};
@ -1432,7 +1444,7 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
/* Fallback. */
{ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"},
{ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
{0, 0, 0, 0}
};
@ -1631,17 +1643,36 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
fprintf_ftype func = info->fprintf_func;
unsigned long mask;
unsigned long value;
unsigned long allowed_arches = ((arm_feature_set *) info->private_data)->coproc;
int cond;
for (insn = coprocessor_opcodes; insn->assembler; insn++)
{
signed long value_in_comment = 0;
const char *c;
if (insn->value == FIRST_IWMMXT_INSN
&& info->mach != bfd_mach_arm_XScale
&& info->mach != bfd_mach_arm_iWMMXt
&& info->mach != bfd_mach_arm_iWMMXt2)
insn = insn + IWMMXT_INSN_COUNT;
if (insn->arch == 0)
switch (insn->value)
{
case SENTINEL_IWMMXT_START:
if (info->mach != bfd_mach_arm_XScale
&& info->mach != bfd_mach_arm_iWMMXt
&& info->mach != bfd_mach_arm_iWMMXt2)
do
insn++;
while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END);
continue;
case SENTINEL_IWMMXT_END:
continue;
case SENTINEL_GENERIC_START:
allowed_arches = ((arm_feature_set *) info->private_data)->core;
continue;
default:
abort ();
}
mask = insn->mask;
value = insn->value;
@ -1677,7 +1708,7 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
if ((given & mask) != value)
continue;
if ((insn->arch & ((arm_feature_set *) info->private_data)->coproc) == 0)
if ((insn->arch & allowed_arches) == 0)
continue;
for (c = insn->assembler; *c; c++)
@ -1691,36 +1722,40 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
break;
case 'A':
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
{
int offset = given & 0xff;
if ((given & (1 << 24)) != 0)
{
int offset = given & 0xff;
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
if (offset)
func (stream, ", #%s%d]%s",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4,
((given & 0x00200000) != 0 ? "!" : ""));
else
value_in_comment = offset * 4;
if ((given & 0x00800000) == 0)
value_in_comment = - value_in_comment;
if ((given & (1 << 24)) != 0)
{
if (offset)
func (stream, ", #%s%d]%s",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4,
((given & 0x00200000) != 0 ? "!" : ""));
else
func (stream, "]");
}
else
{
func (stream, "]");
}
else
{
int offset = given & 0xff;
func (stream, "]");
if (given & (1 << 21))
{
if (offset)
func (stream, ", #%s%d",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4);
}
else
func (stream, ", {%d}", offset);
}
if (given & (1 << 21))
{
if (offset)
func (stream, ", #%s%d",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4);
}
else
func (stream, ", {%d}", offset);
}
}
break;
case 'B':
@ -1880,6 +1915,7 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
break;
case 'd':
func (stream, "%ld", value);
value_in_comment = value;
break;
case 'k':
{
@ -2045,6 +2081,13 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
if (multiplier > 1)
{
value_in_comment = offset * multiplier;
if ((given & 0x00800000) == 0)
value_in_comment = - value_in_comment;
}
if (offset)
{
if ((given & 0x01000000) != 0)
@ -2113,21 +2156,31 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
else
func (stream, "%c", *c);
}
if (value_in_comment > 32 || value_in_comment < -16)
func (stream, "\t; 0x%lx", value_in_comment);
return TRUE;
}
return FALSE;
}
static void
/* Decodes and prints ARM addressing modes. Returns the offset
used in the address, if any, if it is worthwhile printing the
offset as a hexadecimal value in a comment at the end of the
line of disassembly. */
static signed long
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
{
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
int offset = 0;
if (((given & 0x000f0000) == 0x000f0000)
&& ((given & 0x02000000) == 0))
{
int offset = given & 0xfff;
offset = given & 0xfff;
func (stream, "[pc");
@ -2159,6 +2212,7 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
func (stream, "\t; ");
info->print_address_func (offset, info);
offset = 0;
}
else
{
@ -2168,7 +2222,7 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
{
if ((given & 0x02000000) == 0)
{
int offset = given & 0xfff;
offset = given & 0xfff;
if (offset)
func (stream, ", #%s%d",
(((given & 0x00800000) == 0)
@ -2189,7 +2243,7 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
{
if ((given & 0x02000000) == 0)
{
int offset = given & 0xfff;
offset = given & 0xfff;
if (offset)
func (stream, "], #%s%d",
(((given & 0x00800000) == 0)
@ -2206,6 +2260,8 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
}
}
}
return (signed long) offset;
}
/* Print one neon instruction on INFO->STREAM.
@ -2242,6 +2298,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
{
if ((given & insn->mask) == insn->value)
{
signed long value_in_comment = 0;
const char *c;
for (c = insn->assembler; *c; c++)
@ -2589,6 +2646,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
break;
case 'd':
func (stream, "%ld", value);
value_in_comment = value;
break;
case 'e':
func (stream, "%ld", (1ul << width) - value);
@ -2597,7 +2655,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
case 'S':
case 'T':
case 'U':
/* various width encodings */
/* Various width encodings. */
{
int base = 8 << (*c - 'S'); /* 8,16 or 32 */
int limit;
@ -2661,6 +2719,10 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
else
func (stream, "%c", *c);
}
if (value_in_comment > 32 || value_in_comment < -16)
func (stream, "\t; 0x%lx", value_in_comment);
return TRUE;
}
}
@ -2684,11 +2746,6 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
for (insn = arm_opcodes; insn->assembler; insn++)
{
if (insn->value == FIRST_IWMMXT_INSN
&& info->mach != bfd_mach_arm_XScale
&& info->mach != bfd_mach_arm_iWMMXt)
insn = insn + IWMMXT_INSN_COUNT;
if ((given & insn->mask) != insn->value)
continue;
@ -2702,6 +2759,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
|| (insn->mask & 0xF0000000) == 0xF0000000
|| (insn->mask == 0 && insn->value == 0))
{
signed long value_in_comment = 0;
const char *c;
for (c = insn->assembler; *c; c++)
@ -2715,13 +2773,13 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'a':
print_arm_address (pc, info, given);
value_in_comment = print_arm_address (pc, info, given);
break;
case 'P':
/* Set P address bit and use normal address
printing routine. */
print_arm_address (pc, info, given | (1 << 24));
value_in_comment = print_arm_address (pc, info, given | (1 << 24));
break;
case 's':
@ -2747,6 +2805,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
{
/* Immediate. */
int offset = ((given & 0xf00) >> 4) | (given & 0xf);
if (offset)
func (stream, ", #%s%d",
(((given & 0x00800000) == 0)
@ -2771,6 +2830,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
{
/* Immediate. */
int offset = ((given & 0xf00) >> 4) | (given & 0xf);
if (offset)
func (stream, "], #%s%d",
(((given & 0x00800000) == 0)
@ -2793,7 +2853,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
case 'b':
{
int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
info->print_address_func (disp*4 + pc + 8, info);
info->print_address_func (disp * 4 + pc + 8, info);
}
break;
@ -2849,36 +2909,40 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'A':
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
{
int offset = given & 0xff;
if ((given & (1 << 24)) != 0)
{
int offset = given & 0xff;
value_in_comment = offset * 4;
if ((given & 0x00800000) == 0)
value_in_comment = - value_in_comment;
if (offset)
func (stream, ", #%s%d]%s",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4,
((given & 0x00200000) != 0 ? "!" : ""));
else
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
if ((given & (1 << 24)) != 0)
{
if (offset)
func (stream, ", #%s%d]%s",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4,
((given & 0x00200000) != 0 ? "!" : ""));
else
func (stream, "]");
}
else
{
func (stream, "]");
}
else
{
int offset = given & 0xff;
func (stream, "]");
if (given & (1 << 21))
{
if (offset)
func (stream, ", #%s%d",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4);
}
else
func (stream, ", {%d}", offset);
}
if (given & (1 << 21))
{
if (offset)
func (stream, ", #%s%d",
((given & 0x00800000) == 0 ? "-" : ""),
offset * 4);
}
else
func (stream, ", {%d}", offset);
}
}
break;
case 'B':
@ -2944,12 +3008,15 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'd':
func (stream, "%ld", value);
value_in_comment = value;
break;
case 'b':
func (stream, "%ld", value * 8);
value_in_comment = value * 8;
break;
case 'W':
func (stream, "%ld", value + 1);
value_in_comment = value + 1;
break;
case 'x':
func (stream, "0x%08lx", value);
@ -2963,6 +3030,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'X':
func (stream, "%01lx", value & 0xf);
value_in_comment = value;
break;
case '`':
c++;
@ -3026,6 +3094,9 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
else
func (stream, "%c", *c);
}
if (value_in_comment > 32 || value_in_comment < -16)
func (stream, "\t; 0x%lx", value_in_comment);
return;
}
}
@ -3044,7 +3115,9 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
for (insn = thumb_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
{
signed long value_in_comment = 0;
const char *c = insn->assembler;
for (; *c; c++)
{
int domaskpc = 0;
@ -3216,14 +3289,17 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
case 'd':
func (stream, "%ld", reg);
value_in_comment = reg;
break;
case 'H':
func (stream, "%ld", reg << 1);
value_in_comment = reg << 1;
break;
case 'W':
func (stream, "%ld", reg << 2);
value_in_comment = reg << 2;
break;
case 'a':
@ -3232,6 +3308,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
before the calculation. */
info->print_address_func
(((pc + 4) & ~3) + (reg << 2), info);
value_in_comment = 0;
break;
case 'x':
@ -3241,6 +3318,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
case 'B':
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
info->print_address_func (reg * 2 + pc + 4, info);
value_in_comment = 0;
break;
case 'c':
@ -3277,6 +3355,9 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
abort ();
}
}
if (value_in_comment > 32 || value_in_comment < -16)
func (stream, "\t; 0x%lx", value_in_comment);
return;
}
@ -3326,7 +3407,9 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
for (insn = thumb32_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
{
signed long value_in_comment = 0;
const char *c = insn->assembler;
for (; *c; c++)
{
if (*c != '%')
@ -3459,14 +3542,19 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
int offset = 0;
func (stream, "[%s", arm_regnames[Rn]);
if (U) /* 12-bit positive immediate offset */
offset = i12;
else if (Rn == 15) /* 12-bit negative immediate offset */
offset = -(int)i12;
else if (op == 0x0) /* shifted register offset */
if (U) /* 12-bit positive immediate offset. */
{
offset = i12;
if (Rn != 15)
value_in_comment = offset;
}
else if (Rn == 15) /* 12-bit negative immediate offset. */
offset = - (int) i12;
else if (op == 0x0) /* Shifted register offset. */
{
unsigned int Rm = (i8 & 0x0f);
unsigned int sh = (i8 & 0x30) >> 4;
func (stream, ", %s", arm_regnames[Rm]);
if (sh)
func (stream, ", lsl #%u", sh);
@ -3475,30 +3563,30 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
else switch (op)
{
case 0xE: /* 8-bit positive immediate offset */
case 0xE: /* 8-bit positive immediate offset. */
offset = i8;
break;
case 0xC: /* 8-bit negative immediate offset */
case 0xC: /* 8-bit negative immediate offset. */
offset = -i8;
break;
case 0xF: /* 8-bit + preindex with wb */
case 0xF: /* 8-bit + preindex with wb. */
offset = i8;
writeback = TRUE;
break;
case 0xD: /* 8-bit - preindex with wb */
case 0xD: /* 8-bit - preindex with wb. */
offset = -i8;
writeback = TRUE;
break;
case 0xB: /* 8-bit + postindex */
case 0xB: /* 8-bit + postindex. */
offset = i8;
postind = TRUE;
break;
case 0x9: /* 8-bit - postindex */
case 0x9: /* 8-bit - postindex. */
offset = -i8;
postind = TRUE;
break;
@ -3538,7 +3626,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
if (P)
{
if (off || !U)
func (stream, ", #%c%u", U ? '+' : '-', off * 4);
{
func (stream, ", #%c%u", U ? '+' : '-', off * 4);
value_in_comment = off * 4 * U ? 1 : -1;
}
func (stream, "]");
if (W)
func (stream, "!");
@ -3547,7 +3638,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
{
func (stream, "], ");
if (W)
func (stream, "#%c%u", U ? '+' : '-', off * 4);
{
func (stream, "#%c%u", U ? '+' : '-', off * 4);
value_in_comment = off * 4 * U ? 1 : -1;
}
else
func (stream, "{%u}", off);
}
@ -3558,6 +3652,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
{
unsigned int Sbit = (given & 0x01000000) >> 24;
unsigned int type = (given & 0x00600000) >> 21;
switch (type)
{
case 0: func (stream, Sbit ? "sb" : "b"); break;
@ -3722,8 +3817,14 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
switch (*c)
{
case 'd': func (stream, "%lu", val); break;
case 'W': func (stream, "%lu", val * 4); break;
case 'd':
func (stream, "%lu", val);
value_in_comment = val;
break;
case 'W':
func (stream, "%lu", val * 4);
value_in_comment = val * 4;
break;
case 'r': func (stream, "%s", arm_regnames[val]); break;
case 'c':
@ -3757,6 +3858,9 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
abort ();
}
}
if (value_in_comment > 32 || value_in_comment < -16)
func (stream, "\t; 0x%lx", value_in_comment);
return;
}