common/sim-bits.h: Document ROTn macro.
igen/{igen.c,ld-insns.h}: Document mnemonic string formats.
mips/Makefile.in: Add dependencies for files included by mips.igen
mips/vr5400.igen: checkpoint vr5400 instructions.
This commit is contained in:
Andrew Cagney
parent
a0539c6102
commit
01b9cd49ca
8 changed files with 726 additions and 22 deletions
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@ -1,5 +1,7 @@
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Tue Oct 28 12:29:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-bits.h: Document ROTn macro.
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* sim-endian.h (H2T): Handle 16 byte variables.
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* sim-n-core.h (sim_core_read_unaligned_N): Return a dummy when an
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@ -1,3 +1,7 @@
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Wed Oct 29 13:17:17 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* ld-insn.h: Document mnemonic string format.
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Tue Oct 28 10:50:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* gen-icache.c (print_icache_extraction): Force result of atol to
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@ -59,7 +59,7 @@ Things-to-lose:
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Do-last:
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r5900_files="ChangeLog configure configure.in interp.c gencode.c mips.igen mips.dc m16.igen r5900.igen"
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r5900_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen r5900.igen"
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if ( echo $* | grep keep\-r5900 > /dev/null ) ; then
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for i in $r5900_files ; do
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@ -89,7 +89,7 @@ else
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fi
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tx19_files="ChangeLog configure configure.in interp.c gencode.c mips.igen mips.dc m16.igen"
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tx19_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen"
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if ( echo $* | grep keep\-tx19 > /dev/null ) ; then
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for i in $tx19_files ; do
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@ -119,7 +119,7 @@ else
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fi
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vr5400_files="ChangeLog configure configure.in interp.c gencode.c mips.igen mips.dc m16.igen vr5400.igen"
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vr5400_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen vr5400.igen"
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if ( echo $* | grep keep\-vr5400 > /dev/null ) ; then
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for i in $vr5400_files ; do
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@ -170,5 +170,10 @@ never_files="ChangeLog configure configure.in interp.c gencode.c mips.igen mips.
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done
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for i in * ; do
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if test ! -d $i && (grep sanitize $i > /dev/null) ; then
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echo '***' Some mentions of Sanitize are still left in $i! 1>&2
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fi
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done
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# End of file.
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@ -1,3 +1,10 @@
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Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* mips.igen:
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* Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
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(tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
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Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* mips.igen: Add model filter field to records.
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@ -100,7 +100,14 @@ getopt1.o: $(srcdir)/../../libiberty/getopt1.c
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IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
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IGEN_INSN=$(srcdir)/mips.igen
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IGEN_DC=$(srcdir)/mips.dc
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IGEN_INCLUDE=\
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$(start-sanitize-r5900) \
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$(srcdir)/r5900.igen \
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$(end-sanitize-r5900) \
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$(start-sanitize-vr5400) \
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$(srcdir)/vr5400.igen \
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$(end-sanitize-vr5400) \
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$(srcdir)/m16.igen
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SIM_IGEN_ALL = tmp-igen
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@ -128,7 +135,7 @@ clean-igen:
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rm -f $(BUILT_SRC_FROM_IGEN)
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rm -f tmp-igen
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tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen
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tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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cd ../igen && $(MAKE)
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../igen/igen \
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$(IGEN_TRACE) \
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@ -200,7 +207,7 @@ clean-m16:
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rm -f $(BUILT_SRC_FROM_M16)
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rm -f tmp-m16
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tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen
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tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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cd ../igen && $(MAKE)
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../igen/igen \
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$(IGEN_TRACE) \
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@ -612,9 +612,6 @@
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*mipsII:
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*mipsIII:
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*mipsIV:
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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@ -953,7 +950,7 @@
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00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
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"dsll r<RD>, r<RT>, <SA>"
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"dsll r<RD>, r<RT>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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// start-sanitize-vr5400
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@ -967,13 +964,13 @@
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*tx19:
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// end-sanitize-tx19
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{
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int s = SA;
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int s = SHIFT;
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GPR[RD] = GPR[RT] << s;
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}
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00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
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"dsll32 r<RD>, r<RT>, <SA>"
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"dsll32 r<RD>, r<RT>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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// start-sanitize-vr5400
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@ -987,7 +984,7 @@
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*tx19:
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// end-sanitize-tx19
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{
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int s = 32 + SA;
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int s = 32 + SHIFT;
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GPR[RD] = GPR[RT] << s;
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}
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@ -1013,7 +1010,7 @@
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00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
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"dsra r<RD>, r<RT>, <SA>"
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"dsra r<RD>, r<RT>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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// start-sanitize-vr5400
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@ -1027,13 +1024,13 @@
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*tx19:
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// end-sanitize-tx19
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{
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int s = SA;
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int s = SHIFT;
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GPR[RD] = ((signed64) GPR[RT]) >> s;
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}
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00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
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"dsra32 r<RT>, r<RD>, <SA>"
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"dsra32 r<RT>, r<RD>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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// start-sanitize-vr5400
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@ -1047,7 +1044,7 @@
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*tx19:
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// end-sanitize-tx19
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{
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int s = 32 + SA;
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int s = 32 + SHIFT;
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GPR[RD] = ((signed64) GPR[RT]) >> s;
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}
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@ -1073,7 +1070,7 @@
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00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
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"dsrav r<RD>, r<RT>, <SA>"
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"dsrav r<RD>, r<RT>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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// start-sanitize-vr5400
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@ -1087,13 +1084,13 @@
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*tx19:
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// end-sanitize-tx19
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{
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int s = SA;
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int s = SHIFT;
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GPR[RD] = (unsigned64) GPR[RT] >> s;
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}
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00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
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"dsrl32 r<RD>, r<RT>, <SA>"
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"dsrl32 r<RD>, r<RT>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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// start-sanitize-vr5400
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@ -1107,7 +1104,7 @@
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*tx19:
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// end-sanitize-tx19
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{
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int s = 32 + SA;
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int s = 32 + SHIFT;
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GPR[RD] = (unsigned64) GPR[RT] >> s;
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}
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@ -503,6 +503,9 @@ struct _sim_cpu {
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#define SA ((STATE_CPU (sd, 0))->sa)
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/* end-sanitize-r5900 */
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/* start-sanitize-vr5400 */
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/* end-sanitize-vr5400 */
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@ -1 +1,680 @@
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// Empty
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// Integer Instructions
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// --------------------
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//
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// MulAcc is the Multiply Accumulator.
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// This register is mapped on the the HI and LO registers.
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// Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
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// Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
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:function:::unsigned64:MulAcc:
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{
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unsigned64 result = U8_4 (HI, LO);
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return result;
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}
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:function:::void:SET_MulAcc:unsigned64 value
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{
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*AL4_8 (&HI) = VH4_8 (value);
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*AL4_8 (&LO) = VL4_8 (value);
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}
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:function:::signed64:SignedMultiply:signed32 l, signed32 r
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{
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signed64 result = (signed64) l * (signed64) r;
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return result;
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}
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:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
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{
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unsigned64 result = (unsigned64) l * (unsigned64) r;
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return result;
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}
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:function:::unsigned64:Low32Bits:unsigned64 value
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{
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unsigned64 result = VL4_8 (value);
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return result;
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}
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:function:::unsigned64:High32Bits:unsigned64 value
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{
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unsigned64 result = VH4_8 (value);
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return result;
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}
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// Multiply and Move LO.
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000000,5.RS,5.RT,5.RD,00001,011000::::MUL
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"mul r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply and Move Low.
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000000,5.RS,5.RT,5.RD,00001,011001::::MULU
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"mulu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Multiply and Move HI.
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000000,5.RS,5.RT,5.RD,01001,011000::::MULHI
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"mulhi r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply and Move HI.
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000000,5.RS,5.RT,5.RD,01001,011001::::MULHIU
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"mulhiu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Negate and Move LO.
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000000,5.RS,5.RT,5.RD,00011,011000::::MULS
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"muls r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Negate and Move LO.
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000000,5.RS,5.RT,5.RD,00011,011001::::MULSU
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"mulsu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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|
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// Multiply, Negate and Move HI.
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000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI
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"mulshi r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
|
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SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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|
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// Unsigned Multiply, Negate and Move HI.
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000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU
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"mulshiu r<RD>, r<RS>, r<RT>"
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*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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||||
}
|
||||
|
||||
|
||||
// Multiply, Accumulate and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00101,011000::::MACC
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"macc r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply, Accumulate and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00101,011001::::MACCU
|
||||
"maccu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Multiply, Accumulate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01101,011000::::MACCHI
|
||||
"macchi r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply, Accumulate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01101,011001::::MACCHIU
|
||||
"macchiu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
|
||||
}
|
||||
|
||||
// Multiply, Negate, Accumulate and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00111,011000::::MSAC
|
||||
"msac r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply, Negate, Accumulate and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00111,011001::::MSACU
|
||||
"msacu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Multiply, Negate, Accumulate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
|
||||
"msachi r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply, Negate, Accumulate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU
|
||||
"msachiu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
|
||||
// Rotate Right.
|
||||
000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR
|
||||
"ror r<RD>, r<RT>, <SHIFT>"
|
||||
*vr5400:
|
||||
{
|
||||
int s = SHIFT;
|
||||
GPR[RD] = ROTR32 (GPR[RT], s);
|
||||
}
|
||||
|
||||
// Rotate Right Variable.
|
||||
000000,5.RS,5.RT,5.RD,00001,000110::::RORV
|
||||
"rorv r<RD>, r<RT>, <RS>"
|
||||
*vr5400:
|
||||
{
|
||||
int s = MASKED (GPR[RS], 4, 0);
|
||||
GPR[RD] = ROTR32 (GPR[RT], s);
|
||||
}
|
||||
|
||||
// Double Rotate Right.
|
||||
000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR
|
||||
"dror r<RD>, r<RT>, <SHIFT>"
|
||||
*vr5400:
|
||||
{
|
||||
int s = SHIFT;
|
||||
GPR[RD] = ROTR64 (GPR[RT], s);
|
||||
}
|
||||
|
||||
// Double Rotate Right Plus 32.
|
||||
000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32
|
||||
"dror32 r<RD>, r<RT>, <SHIFT>"
|
||||
*vr5400:
|
||||
{
|
||||
int s = SHIFT + 32;
|
||||
GPR[RD] = ROTR64 (GPR[RT], s);
|
||||
}
|
||||
|
||||
// Double Rotate Right Variable.
|
||||
000000,5.RS,5.RT,5.RD,00001,010110::::DRORV
|
||||
"drorv r<RD>, r<RT>, <RS>"
|
||||
*vr5400:
|
||||
{
|
||||
int s = MASKED (GPR[RS], 5, 0);
|
||||
GPR[RD] = ROTR64 (GPR[RT], s);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// Media Instructions
|
||||
// ------------------
|
||||
|
||||
// Note: Vector unit in R5400 supports only octal byte format.
|
||||
// Note: The sel field is deduced by special handling of the "vt"
|
||||
// operand.
|
||||
// If vt is:
|
||||
// of the form $vt[0], then sel is 0000
|
||||
// of the form $vt[1], then sel is 0001
|
||||
// of the form $vt[2], then sel is 0010
|
||||
// of the form $vt[3], then sel is 0011
|
||||
// of the form $vt[4], then sel is 0100
|
||||
// of the form $vt[5], then sel is 0101
|
||||
// of the form $vt[6], then sel is 0110
|
||||
// of the form $vt[7], then sel is 0111
|
||||
// Normal register specifier, then sel is 1011
|
||||
// Constant, then sel is 1111
|
||||
//
|
||||
// VecAcc is the Vector Accumulator.
|
||||
// This accumulator is organized as 8X24 bit (192 bit) register.
|
||||
// This accumulator holds only signed values.
|
||||
|
||||
:function:::signed:vr:int fpr, int byte
|
||||
{
|
||||
signed8 b = V1_8 (value_fpr (sd, fpr, fmt_long), byte);
|
||||
return b;
|
||||
}
|
||||
|
||||
:function:::void:set_vr:int fpr, int byte, signed value
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
:function:::signed:VecAcc:int byte
|
||||
{
|
||||
abort ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
:function:::void:set_VecAcc:int byte, signed value
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
:function:::int:cc:int i
|
||||
{
|
||||
abort ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
:function:::void:set_cc:int i, int value
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
:function:::signed:Min:signed l, signed r
|
||||
{
|
||||
if (l < r)
|
||||
return l;
|
||||
else
|
||||
return r;
|
||||
}
|
||||
|
||||
:function:::signed:Max:signed l, signed r
|
||||
{
|
||||
if (l < r)
|
||||
return r;
|
||||
else
|
||||
return l;
|
||||
}
|
||||
|
||||
:function:::signed:Compare:signed l, signed r
|
||||
{
|
||||
abort ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
:function:::signed:Clamp:signed l
|
||||
{
|
||||
abort ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
:function:::signed:Round:signed l
|
||||
{
|
||||
abort ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
:function:::void:ByteAlign:int vd, int imm, int vs, int vt
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
:function:::signed:One_of:int vs, int vt
|
||||
{
|
||||
abort ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
:function:::unsigned:select:int i, int sel, int vt
|
||||
{
|
||||
if (sel < 8)
|
||||
return vr (SD_, vt, sel);
|
||||
else if (sel == 0x13)
|
||||
return vr (SD_, vt, i);
|
||||
else if (sel == 0x1f)
|
||||
return vt;
|
||||
else
|
||||
semantic_illegal (sd, cia);
|
||||
return 0;
|
||||
}
|
||||
|
||||
:%s::::VT:int sel, int vt
|
||||
{
|
||||
static char buf[20];
|
||||
if (sel < 8)
|
||||
sprintf (buf, "v%d[%d]", vt, sel);
|
||||
else if (sel == 0x13)
|
||||
sprintf (buf, "v%d", vt);
|
||||
else if (sel == 0x1f)
|
||||
sprintf (buf, "%d", vt);
|
||||
else
|
||||
sprintf (buf, "(invalid)");
|
||||
return buf;
|
||||
}
|
||||
|
||||
|
||||
// Vector Add.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,001011::::ADD.OB
|
||||
"add.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) + select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Align.
|
||||
010010,00,3.IMM,5.VT,5.VS,5.VD,011000::::ALNI.OB
|
||||
"alni.ob v<VD>, v<VS>, v<VT>, <IMM>"
|
||||
*vr5400:
|
||||
{
|
||||
ByteAlign (SD_, VD, IMM, VS, VT);
|
||||
}
|
||||
|
||||
// Vector And.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,001100::::AND.OB
|
||||
"and.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) & select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Compare Equal.
|
||||
010010,4.SEL,0,5.VT,5.VS,00000,000001::::C.EQ.OB
|
||||
"c.eq.ob v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), select (SD_, i, SEL, VT)));
|
||||
}
|
||||
|
||||
// Vector Compare Less Than or Equal.
|
||||
010010,4.SEL,0,5.VT,5.VS,00000,000101::::C.LE.OB
|
||||
"c.le.ob v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), select (SD_, i, SEL, VT)));
|
||||
}
|
||||
|
||||
// Vector Compare Less Than.
|
||||
010010,4.SEL,0,5.VT,5.VS,00000,000100::::C.LT.OB
|
||||
"c.lt.ob v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), select (SD_, i, SEL, VT)));
|
||||
}
|
||||
|
||||
// Vector Maximum.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,000111::::MAX.OB
|
||||
"max.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, Max (SD_, vr (SD_, VS, i), select (SD_, i, SEL, VT)));
|
||||
}
|
||||
|
||||
// Vector Minimum.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,000110::::MIN.OB
|
||||
"min.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, Min (SD_, vr (SD_, VS, i), select (SD_, i, SEL, VT)));
|
||||
}
|
||||
|
||||
// Vector Multiply.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,110000::::MUL.OB
|
||||
"mul.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) * select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Multiply, Accumulate.
|
||||
010010,4.SEL,0,5.VT,5.VS,00000,110011::::MULA.OB
|
||||
"mula.ob v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_VecAcc (SD_, i, VecAcc (SD_, i) + vr (SD_, VS, i) * select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Multiply, Load Accumulator.
|
||||
010010,4.SEL,0,5.VT,5.VS,10000,110011::::MULL.OB
|
||||
"mull.ob v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_VecAcc (SD_, i, 0 + vr (SD_, VS, i) * select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Multiply, Negate, Accumulate.
|
||||
010010,4.SEL,0,5.VT,5.VS,00000,110010::::MULS.OB
|
||||
"muls.ob v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_VecAcc (SD_, i, VecAcc (SD_, i) - vr (SD_, VS, i) * select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Multiply, Negate, Load Accumulator.
|
||||
010010,4.SEL,0,5.VT,5.VS,10000,110010::::MULSL.OB
|
||||
"mulsl.ob v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_VecAcc (SD_, i, 0 - vr (SD_, VS, i) * select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector NOr.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,001111::::NOR.OB
|
||||
"nor.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, ! (vr (SD_, VS, i) | select (SD_, i, SEL, VT)));
|
||||
}
|
||||
|
||||
// Vector Or.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,001110::::OR.OB
|
||||
"or.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) | select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Pick False.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,000010::::PICKF.OB
|
||||
"pickf.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, cc (SD_, i) ? select (SD_, i, SEL, VT) : vr (SD_, VS, i));
|
||||
}
|
||||
|
||||
// Vector Pick True.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,000011::::PICKT.OB
|
||||
"pickt.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, cc (SD_, i) ? vr (SD_, VS, i) : select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Read Accumulator High.
|
||||
010010,1000,0,00000,00000,5.VD,111111::::RACH.OB
|
||||
"rach.ob v<VD>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 23, 16));
|
||||
}
|
||||
|
||||
// Vector Read Accumulator Low.
|
||||
010010,0000,0,00000,00000,5.VD,111111::::RACL.OB
|
||||
"racl.ob v<VD>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 7, 0));
|
||||
}
|
||||
|
||||
// Vector Read Accumulator Middle.
|
||||
010010,0100,0,00000,00000,5.VD,111111::::RACM.OB
|
||||
"racm.ob v<VD>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 15, 8));
|
||||
}
|
||||
|
||||
// Vector Scale, Round and Clamp Accumulator.
|
||||
010010,4.SEL,0,5.VT,00000,5.VD,100000::::RZU.OB
|
||||
"rzu.ob v<VD>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, Clamp (SD_, Round (SD_, VecAcc (SD_, i) >> select (SD_, i, SEL, VT))));
|
||||
}
|
||||
|
||||
// Vector Element Shuffle.
|
||||
010010,0110,0,5.VT,5.VS,5.VD,011111::::SHFL.MIXH.OB
|
||||
"shfl.mixh.ob v<VD>, v<VS>, <VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
||||
}
|
||||
|
||||
// Vector Element Shuffle.
|
||||
010010,0111,0,5.VT,5.VS,5.VD,011111::::SHFL.MIXL.OB
|
||||
"shfl.mixl.ob v<VD>, v<VS>, <VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
||||
}
|
||||
|
||||
// Vector Element Shuffle.
|
||||
010010,0100,0,5.VT,5.VS,5.VD,011111::::SHFL.PACH.OB
|
||||
"shfl.pach.ob v<VD>, v<VS>, <VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
||||
}
|
||||
|
||||
// Vector Element Shuffle.
|
||||
010010,0101,0,5.VT,5.VS,5.VD,011111::::SHFL.PACL.OB
|
||||
"shfl.pacl.ob v<VD>, v<VS>, <VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
||||
}
|
||||
|
||||
// Vector Shift Left Logical.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,010000::::SLL.OB
|
||||
"sll.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) << select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Shift Right Logical.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,010010::::SRL.OB
|
||||
"srl.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) >> select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Subtract.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,001010::::SUB.OB
|
||||
"sub.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) - select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Write Accumulator High.
|
||||
010010,1000,0,00000,5.VS,00000,111110::::WACH.OB
|
||||
"wach.ob v<VS>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
/* High8 */ set_VecAcc (SD_, i, (vr (SD_, VS, i) << 16) | MASKED (VecAcc (SD_, i), 15, 0));
|
||||
}
|
||||
|
||||
// Vector Write Accumulator Low.
|
||||
010010,0000,0,5.VT,5.VS,00000,111110::::WACL.OB
|
||||
"wacl.ob v<VS>, <VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_VecAcc (SD_, i, (EXTEND8 (vr (SD_, VS, i)) << 8) | vr (SD_, VT, i));
|
||||
}
|
||||
|
||||
// Vector XOr.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,001101::::XOR.OB
|
||||
"xor.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) ^ select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue