FreeChainXenon/binutils-gdb
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

gas/

Browse source 
* config/tc-arm.c (s_arm_unwind_save_core): Don't emit an extra
	opcode if r4-r15 are not saved.
gas/testsuite/
	* gas/arm/unwind.s, gas/arm/unwind.d, gas/arm/unwind_vxworks.d: Add
	a test for saving only the low registers.
This commit is contained in:
Daniel Jacobowitz 2005-11-15 14:29:58 +00:00
parent b33a619050
commit 01ae4198c0
6 changed files with 49 additions and 26 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
gas/ChangeLog
View file

@ -1,3 +1,8 @@
2005-11-15 Daniel Jacobowitz <dan@codesourcery.com>
* config/tc-arm.c (s_arm_unwind_save_core): Don't emit an extra
opcode if r4-r15 are not saved.
2005-11-15 Alan Modra <amodra@bigpond.net.au>
* symbols.c (S_GET_VALUE): Remove non-BFD assembler recursion guard.

48
gas/config/tc-arm.c
View file

@ -2249,30 +2249,34 @@ s_arm_unwind_save_core (void)
unwind.pending_offset = 0;
}
/* See if we can use the short opcodes. These pop a block of upto 8
registers starting with r4, plus maybe r14. */
for (n = 0; n < 8; n++)
/* Pop r4-r15. */
if (range & 0xfff0)
{
/* Break at the first non-saved register. */
if ((range & (1 << (n + 4))) == 0)
break;
}
/* See if there are any other bits set. */
if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
{
/* Use the long form. */
op = 0x8000 | ((range >> 4) & 0xfff);
add_unwind_opcode (op, 2);
}
else
{
/* Use the short form. */
if (range & 0x4000)
op = 0xa8; /* Pop r14. */
/* See if we can use the short opcodes. These pop a block of up to 8
registers starting with r4, plus maybe r14. */
for (n = 0; n < 8; n++)
{
/* Break at the first non-saved register. */
if ((range & (1 << (n + 4))) == 0)
break;
}
/* See if there are any other bits set. */
if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
{
/* Use the long form. */
op = 0x8000 | ((range >> 4) & 0xfff);
add_unwind_opcode (op, 2);
}
else
op = 0xa0; /* Do not pop r14. */
op |= (n - 1);
add_unwind_opcode (op, 1);
{
/* Use the short form. */
if (range & 0x4000)
op = 0xa8; /* Pop r14. */
else
op = 0xa0; /* Do not pop r14. */
op |= (n - 1);
add_unwind_opcode (op, 1);
}
}
/* Pop r0-r3. */

5
gas/testsuite/ChangeLog
View file

@ -1,3 +1,8 @@
2005-11-15 Daniel Jacobowitz <dan@codesourcery.com>
* gas/arm/unwind.s, gas/arm/unwind.d, gas/arm/unwind_vxworks.d: Add
a test for saving only the low registers.
2005-11-14 Thiemo Seufer <ths@networkno.de>
* gas/testsuite/gas/mips/mips16e-jrc.d: Tighten file format

5
gas/testsuite/gas/arm/unwind.d
View file

@ -24,11 +24,12 @@ OFFSET TYPE VALUE
00000018 R_ARM_PREL31 .text.*
0000001c R_ARM_PREL31 .ARM.extab.*
00000020 R_ARM_PREL31 .text.*
00000028 R_ARM_PREL31 .text.*
Contents of section .text:
0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003) .*
0010 (0420|2004) .*
0010 (04200520|20052004) .*
Contents of section .ARM.extab:
0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000 .*
0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600) .*
@ -36,6 +37,6 @@ Contents of section .ARM.extab:
Contents of section .ARM.exidx:
0000 00000000 (b0b0a880 04000000|80a8b0b0 00000004) 00000000 .*
0010 (08000000 0c000000 0c000000 1c000000|00000008 0000000c 0000000c 0000001c) .*
0020 (10000000 08849780|00000010 80978408) .*
0020 (10000000 08849780 12000000 b00fb180|00000010 80978408 00000012 80b10fb0) .*
# Ignore .ARM.attributes section
#...

5
gas/testsuite/gas/arm/unwind.s
View file

@ -44,3 +44,8 @@ foo4: @ Thumb frame pointer
@sub sp, sp, #8
mov r0, #4
.fnend
foo5: @ Save r0-r3 only.
.fnstart
.save {r0, r1, r2, r3}
mov r0, #5
.fnend

7
gas/testsuite/gas/arm/unwind_vxworks.d
View file

@ -25,11 +25,12 @@ OFFSET TYPE VALUE
00000018 R_ARM_PREL31 .text.*
0000001c R_ARM_PREL31 .ARM.extab.*
00000020 R_ARM_PREL31 .text.*
00000028 R_ARM_PREL31 .text.*
Contents of section .text:
0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003) .*
0010 (0420|2004) .*
0010 (04200520|20052004) .*
Contents of section .ARM.extab:
0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000 .*
0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600) .*
@ -37,4 +38,6 @@ Contents of section .ARM.extab:
Contents of section .ARM.exidx:
0000 00000000 (b0b0a880 00000000|80a8b0b0 00000000) 00000000 .*
0010 00000000 00000000 00000000 00000000 .*
0020 (00000000 08849780|00000000 80978408) .*
0020 (00000000 08849780 00000000 b00fb180|00000000 80978408 00000000 80b10fb0) .*
# Ignore .ARM.attributes section
#...