2018-07-25 10:43:22 +01:00
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/* Target-dependent code for the CSKY architecture, for GDB.
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2023-01-01 16:49:04 +04:00
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Copyright (C) 2010-2023 Free Software Foundation, Inc.
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2018-07-25 10:43:22 +01:00
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Contributed by C-SKY Microsystems and Mentor Graphics.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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Rename common to gdbsupport
This is the next patch in the ongoing series to move gdbsever to the
top level.
This patch just renames the "common" directory. The idea is to do
this move in two parts: first rename the directory (this patch), then
move the directory to the top. This approach makes the patches a bit
more tractable.
I chose the name "gdbsupport" for the directory. However, as this
patch was largely written by sed, we could pick a new name without too
much difficulty.
Tested by the buildbot.
gdb/ChangeLog
2019-07-09 Tom Tromey <tom@tromey.com>
* contrib/ari/gdb_ari.sh: Change common to gdbsupport.
* configure: Rebuild.
* configure.ac: Change common to gdbsupport.
* gdbsupport: Rename from common.
* acinclude.m4: Change common to gdbsupport.
* Makefile.in (CONFIG_SRC_SUBDIR, COMMON_SFILES)
(HFILES_NO_SRCDIR, stamp-version, ALLDEPFILES): Change common to
gdbsupport.
* aarch64-tdep.c, ada-lang.c, ada-lang.h, agent.c, alloc.c,
amd64-darwin-tdep.c, amd64-dicos-tdep.c, amd64-fbsd-nat.c,
amd64-fbsd-tdep.c, amd64-linux-nat.c, amd64-linux-tdep.c,
amd64-nbsd-tdep.c, amd64-obsd-tdep.c, amd64-sol2-tdep.c,
amd64-tdep.c, amd64-windows-tdep.c, arch-utils.c,
arch/aarch64-insn.c, arch/aarch64.c, arch/aarch64.h, arch/amd64.c,
arch/amd64.h, arch/arm-get-next-pcs.c, arch/arm-linux.c,
arch/arm.c, arch/i386.c, arch/i386.h, arch/ppc-linux-common.c,
arch/riscv.c, arch/riscv.h, arch/tic6x.c, arm-tdep.c, auto-load.c,
auxv.c, ax-gdb.c, ax-general.c, ax.h, breakpoint.c, breakpoint.h,
btrace.c, btrace.h, build-id.c, build-id.h, c-lang.h, charset.c,
charset.h, cli/cli-cmds.c, cli/cli-cmds.h, cli/cli-decode.c,
cli/cli-dump.c, cli/cli-option.h, cli/cli-script.c,
coff-pe-read.c, command.h, compile/compile-c-support.c,
compile/compile-c.h, compile/compile-cplus-symbols.c,
compile/compile-cplus-types.c, compile/compile-cplus.h,
compile/compile-loc2c.c, compile/compile.c, completer.c,
completer.h, contrib/ari/gdb_ari.sh, corefile.c, corelow.c,
cp-support.c, cp-support.h, cp-valprint.c, csky-tdep.c, ctf.c,
darwin-nat.c, debug.c, defs.h, disasm-selftests.c, disasm.c,
disasm.h, dtrace-probe.c, dwarf-index-cache.c,
dwarf-index-cache.h, dwarf-index-write.c, dwarf2-frame.c,
dwarf2expr.c, dwarf2loc.c, dwarf2read.c, event-loop.c,
event-top.c, exceptions.c, exec.c, extension.h, fbsd-nat.c,
features/aarch64-core.c, features/aarch64-fpu.c,
features/aarch64-pauth.c, features/aarch64-sve.c,
features/i386/32bit-avx.c, features/i386/32bit-avx512.c,
features/i386/32bit-core.c, features/i386/32bit-linux.c,
features/i386/32bit-mpx.c, features/i386/32bit-pkeys.c,
features/i386/32bit-segments.c, features/i386/32bit-sse.c,
features/i386/64bit-avx.c, features/i386/64bit-avx512.c,
features/i386/64bit-core.c, features/i386/64bit-linux.c,
features/i386/64bit-mpx.c, features/i386/64bit-pkeys.c,
features/i386/64bit-segments.c, features/i386/64bit-sse.c,
features/i386/x32-core.c, features/riscv/32bit-cpu.c,
features/riscv/32bit-csr.c, features/riscv/32bit-fpu.c,
features/riscv/64bit-cpu.c, features/riscv/64bit-csr.c,
features/riscv/64bit-fpu.c, features/tic6x-c6xp.c,
features/tic6x-core.c, features/tic6x-gp.c, filename-seen-cache.h,
findcmd.c, findvar.c, fork-child.c, gcore.c, gdb_bfd.c, gdb_bfd.h,
gdb_proc_service.h, gdb_regex.c, gdb_select.h, gdb_usleep.c,
gdbarch-selftests.c, gdbthread.h, gdbtypes.h, gnu-nat.c,
go32-nat.c, guile/guile.c, guile/scm-ports.c,
guile/scm-safe-call.c, guile/scm-type.c, i386-fbsd-nat.c,
i386-fbsd-tdep.c, i386-go32-tdep.c, i386-linux-nat.c,
i386-linux-tdep.c, i386-tdep.c, i387-tdep.c,
ia64-libunwind-tdep.c, ia64-linux-nat.c, inf-child.c,
inf-ptrace.c, infcall.c, infcall.h, infcmd.c, inferior-iter.h,
inferior.c, inferior.h, inflow.c, inflow.h, infrun.c, infrun.h,
inline-frame.c, language.h, linespec.c, linux-fork.c, linux-nat.c,
linux-tdep.c, linux-thread-db.c, location.c, machoread.c,
macrotab.h, main.c, maint.c, maint.h, memattr.c, memrange.h,
mi/mi-cmd-break.h, mi/mi-cmd-env.c, mi/mi-cmd-stack.c,
mi/mi-cmd-var.c, mi/mi-interp.c, mi/mi-main.c, mi/mi-parse.h,
minsyms.c, mips-linux-tdep.c, namespace.h,
nat/aarch64-linux-hw-point.c, nat/aarch64-linux-hw-point.h,
nat/aarch64-linux.c, nat/aarch64-sve-linux-ptrace.c,
nat/amd64-linux-siginfo.c, nat/fork-inferior.c,
nat/linux-btrace.c, nat/linux-btrace.h, nat/linux-namespaces.c,
nat/linux-nat.h, nat/linux-osdata.c, nat/linux-personality.c,
nat/linux-procfs.c, nat/linux-ptrace.c, nat/linux-ptrace.h,
nat/linux-waitpid.c, nat/mips-linux-watch.c,
nat/mips-linux-watch.h, nat/ppc-linux.c, nat/x86-dregs.c,
nat/x86-dregs.h, nat/x86-linux-dregs.c, nat/x86-linux.c,
nto-procfs.c, nto-tdep.c, objfile-flags.h, objfiles.c, objfiles.h,
obsd-nat.c, observable.h, osdata.c, p-valprint.c, parse.c,
parser-defs.h, ppc-linux-nat.c, printcmd.c, probe.c, proc-api.c,
procfs.c, producer.c, progspace.h, psymtab.h,
python/py-framefilter.c, python/py-inferior.c, python/py-ref.h,
python/py-type.c, python/python.c, record-btrace.c, record-full.c,
record.c, record.h, regcache-dump.c, regcache.c, regcache.h,
remote-fileio.c, remote-fileio.h, remote-sim.c, remote.c,
riscv-tdep.c, rs6000-aix-tdep.c, rust-exp.y, s12z-tdep.c,
selftest-arch.c, ser-base.c, ser-event.c, ser-pipe.c, ser-tcp.c,
ser-unix.c, skip.c, solib-aix.c, solib-target.c, solib.c,
source-cache.c, source.c, source.h, sparc-nat.c, spu-linux-nat.c,
stack.c, stap-probe.c, symfile-add-flags.h, symfile.c, symfile.h,
symtab.c, symtab.h, target-descriptions.c, target-descriptions.h,
target-memory.c, target.c, target.h, target/waitstatus.c,
target/waitstatus.h, thread-iter.h, thread.c, tilegx-tdep.c,
top.c, top.h, tracefile-tfile.c, tracefile.c, tracepoint.c,
tracepoint.h, tui/tui-io.c, ui-file.c, ui-out.h,
unittests/array-view-selftests.c,
unittests/child-path-selftests.c, unittests/cli-utils-selftests.c,
unittests/common-utils-selftests.c,
unittests/copy_bitwise-selftests.c, unittests/environ-selftests.c,
unittests/format_pieces-selftests.c,
unittests/function-view-selftests.c,
unittests/lookup_name_info-selftests.c,
unittests/memory-map-selftests.c, unittests/memrange-selftests.c,
unittests/mkdir-recursive-selftests.c,
unittests/observable-selftests.c,
unittests/offset-type-selftests.c, unittests/optional-selftests.c,
unittests/parse-connection-spec-selftests.c,
unittests/ptid-selftests.c, unittests/rsp-low-selftests.c,
unittests/scoped_fd-selftests.c,
unittests/scoped_mmap-selftests.c,
unittests/scoped_restore-selftests.c,
unittests/string_view-selftests.c, unittests/style-selftests.c,
unittests/tracepoint-selftests.c, unittests/unpack-selftests.c,
unittests/utils-selftests.c, unittests/xml-utils-selftests.c,
utils.c, utils.h, valarith.c, valops.c, valprint.c, value.c,
value.h, varobj.c, varobj.h, windows-nat.c, x86-linux-nat.c,
xml-support.c, xml-support.h, xml-tdesc.h, xstormy16-tdep.c,
xtensa-linux-nat.c, dwarf2read.h: Change common to gdbsupport.
gdb/gdbserver/ChangeLog
2019-07-09 Tom Tromey <tom@tromey.com>
* configure: Rebuild.
* configure.ac: Change common to gdbsupport.
* acinclude.m4: Change common to gdbsupport.
* Makefile.in (SFILES, OBS, GDBREPLAY_OBS, IPA_OBJS)
(version-generated.c, gdbsupport/%-ipa.o, gdbsupport/%.o): Change
common to gdbsupport.
* ax.c, event-loop.c, fork-child.c, gdb_proc_service.h,
gdbreplay.c, gdbthread.h, hostio-errno.c, hostio.c, i387-fp.c,
inferiors.c, inferiors.h, linux-aarch64-tdesc-selftest.c,
linux-amd64-ipa.c, linux-i386-ipa.c, linux-low.c,
linux-tic6x-low.c, linux-x86-low.c, linux-x86-tdesc-selftest.c,
linux-x86-tdesc.c, lynx-i386-low.c, lynx-low.c, mem-break.h,
nto-x86-low.c, regcache.c, regcache.h, remote-utils.c, server.c,
server.h, spu-low.c, symbol.c, target.h, tdesc.c, tdesc.h,
thread-db.c, tracepoint.c, win32-i386-low.c, win32-low.c: Change
common to gdbsupport.
2019-05-05 20:29:24 -06:00
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#include "gdbsupport/gdb_assert.h"
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2018-07-25 10:43:22 +01:00
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#include "frame.h"
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2019-04-02 20:04:24 -06:00
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#include "inferior.h"
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2019-04-06 13:38:10 -06:00
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#include "symtab.h"
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#include "value.h"
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#include "gdbcmd.h"
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2019-04-02 20:04:24 -06:00
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#include "language.h"
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2019-04-06 13:38:10 -06:00
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#include "gdbcore.h"
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#include "symfile.h"
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2019-04-02 20:04:24 -06:00
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#include "objfiles.h"
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2019-04-06 13:38:10 -06:00
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#include "gdbtypes.h"
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#include "target.h"
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#include "arch-utils.h"
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2019-04-02 20:04:24 -06:00
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#include "regcache.h"
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2019-04-06 13:38:10 -06:00
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#include "osabi.h"
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#include "block.h"
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2018-07-25 10:43:22 +01:00
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#include "reggroups.h"
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2019-04-06 13:38:10 -06:00
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#include "elf/csky.h"
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#include "elf-bfd.h"
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2019-04-02 20:04:24 -06:00
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#include "symcat.h"
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2019-04-06 13:38:10 -06:00
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#include "sim-regno.h"
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#include "dis-asm.h"
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#include "frame-unwind.h"
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#include "frame-base.h"
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2019-04-02 20:04:24 -06:00
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#include "trad-frame.h"
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2019-04-06 13:38:10 -06:00
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#include "infcall.h"
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#include "floatformat.h"
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#include "remote.h"
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#include "target-descriptions.h"
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Move DWARF code to dwarf2/ subdirectory
This moves all the remaining DWARF code to the new dwarf2
subdirectory. This is just a simple renaming, with updates to
includes as needed.
gdb/ChangeLog
2020-02-08 Tom Tromey <tom@tromey.com>
* dwarf2/expr.c: Rename from dwarf2expr.c.
* dwarf2/expr.h: Rename from dwarf2expr.h.
* dwarf2/frame-tailcall.c: Rename from dwarf2-frame-tailcall.c.
* dwarf2/frame-tailcall.h: Rename from dwarf2-frame-tailcall.h.
* dwarf2/frame.c: Rename from dwarf2-frame.c.
* dwarf2/frame.h: Rename from dwarf2-frame.h.
* dwarf2/index-cache.c: Rename from dwarf-index-cache.c.
* dwarf2/index-cache.h: Rename from dwarf-index-cache.h.
* dwarf2/index-common.c: Rename from dwarf-index-common.c.
* dwarf2/index-common.h: Rename from dwarf-index-common.h.
* dwarf2/index-write.c: Rename from dwarf-index-write.c.
* dwarf2/index-write.h: Rename from dwarf-index-write.h.
* dwarf2/loc.c: Rename from dwarf2loc.c.
* dwarf2/loc.h: Rename from dwarf2loc.h.
* dwarf2/read.c: Rename from dwarf2read.c.
* dwarf2/read.h: Rename from dwarf2read.h.
* dwarf2/abbrev.c, aarch64-tdep.c, alpha-tdep.c,
amd64-darwin-tdep.c, arc-tdep.c, arm-tdep.c, bfin-tdep.c,
compile/compile-c-symbols.c, compile/compile-cplus-symbols.c,
compile/compile-loc2c.c, cris-tdep.c, csky-tdep.c, findvar.c,
gdbtypes.c, guile/scm-type.c, h8300-tdep.c, hppa-bsd-tdep.c,
hppa-linux-tdep.c, i386-darwin-tdep.c, i386-linux-tdep.c,
i386-tdep.c, iq2000-tdep.c, m32c-tdep.c, m68hc11-tdep.c,
m68k-tdep.c, microblaze-tdep.c, mips-tdep.c, mn10300-tdep.c,
msp430-tdep.c, nds32-tdep.c, nios2-tdep.c, or1k-tdep.c,
riscv-tdep.c, rl78-tdep.c, rs6000-tdep.c, rx-tdep.c, s12z-tdep.c,
s390-tdep.c, score-tdep.c, sh-tdep.c, sparc-linux-tdep.c,
sparc-tdep.c, sparc64-linux-tdep.c, sparc64-tdep.c, tic6x-tdep.c,
tilegx-tdep.c, v850-tdep.c, xstormy16-tdep.c, xtensa-tdep.c:
Update.
* Makefile.in (COMMON_SFILES): Update.
(HFILES_NO_SRCDIR): Update.
Change-Id: Ied9ce1436cd27ac4a4cffef10ec92e396f181928
2020-02-08 13:40:54 -07:00
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#include "dwarf2/frame.h"
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2018-07-25 10:43:22 +01:00
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#include "user-regs.h"
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#include "valprint.h"
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2019-04-06 13:38:10 -06:00
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#include "csky-tdep.h"
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#include "regset.h"
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#include "opcode/csky.h"
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#include <algorithm>
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#include <vector>
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2018-07-25 10:43:22 +01:00
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/* Control debugging information emitted in this file. */
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gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
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Change boolean options to bool instead of int
This is for add_setshow_boolean_cmd as well as the gdb::option interface.
gdb/ChangeLog:
2019-09-17 Christian Biesinger <cbiesinger@google.com>
* ada-lang.c (ada_ignore_descriptive_types_p): Change to bool.
(print_signatures): Likewise.
(trust_pad_over_xvs): Likewise.
* arch/aarch64-insn.c (aarch64_debug): Likewise.
* arch/aarch64-insn.h (aarch64_debug): Likewise.
* arm-linux-nat.c (arm_apcs_32): Likewise.
* arm-linux-tdep.c (arm_apcs_32): Likewise.
* arm-nbsd-nat.c (arm_apcs_32): Likewise.
* arm-tdep.c (arm_debug): Likewise.
(arm_apcs_32): Likewise.
* auto-load.c (debug_auto_load): Likewise.
(auto_load_gdb_scripts): Likewise.
(global_auto_load): Likewise.
(auto_load_local_gdbinit): Likewise.
(auto_load_local_gdbinit_loaded): Likewise.
* auto-load.h (global_auto_load): Likewise.
(auto_load_local_gdbinit): Likewise.
(auto_load_local_gdbinit_loaded): Likewise.
* breakpoint.c (disconnected_dprintf): Likewise.
(breakpoint_proceeded): Likewise.
(automatic_hardware_breakpoints): Likewise.
(always_inserted_mode): Likewise.
(target_exact_watchpoints): Likewise.
(_initialize_breakpoint): Update.
* breakpoint.h (target_exact_watchpoints): Change to bool.
* btrace.c (maint_btrace_pt_skip_pad): Likewise.
* cli/cli-cmds.c (trace_commands): Likewise.
* cli/cli-cmds.h (trace_commands): Likewise.
* cli/cli-decode.c (add_setshow_boolean_cmd): Change int* argument
to bool*.
* cli/cli-logging.c (logging_overwrite): Change to bool.
(logging_redirect): Likewise.
(debug_redirect): Likewise.
* cli/cli-option.h (option_def) <boolean>: Change return type to bool*.
(struct boolean_option_def) <get_var_address_cb_>: Change return type
to bool.
<boolean_option_def>: Update.
(struct flag_option_def): Change default type of Context to bool
from int.
<flag_option_def>: Change return type of var_address_cb_ to bool*.
* cli/cli-setshow.c (do_set_command): Cast to bool* instead of int*.
(get_setshow_command_value_string): Likewise.
* cli/cli-style.c (cli_styling): Change to bool.
(source_styling): Likewise.
* cli/cli-style.h (source_styling): Likewise.
(cli_styling): Likewise.
* cli/cli-utils.h (struct qcs_flags) <quiet, cont, silent>: Change
to bool.
* command.h (var_types): Update comment.
(add_setshow_boolean_cmd): Change int* var argument to bool*.
* compile/compile-cplus-types.c (debug_compile_cplus_types): Change to
bool.
(debug_compile_cplus_scopes): Likewise.
* compile/compile-internal.h (compile_debug): Likewise.
* compile/compile.c (compile_debug): Likewise.
(struct compile_options) <raw>: Likewise.
* cp-support.c (catch_demangler_crashes): Likewise.
* cris-tdep.c (usr_cmd_cris_version_valid): Likewise.
(usr_cmd_cris_dwarf2_cfi): Likewise.
* csky-tdep.c (csky_debug): Likewise.
* darwin-nat.c (enable_mach_exceptions): Likewise.
* dcache.c (dcache_enabled_p): Likewise.
* defs.h (info_verbose): Likewise.
* demangle.c (demangle): Likewise.
(asm_demangle): Likewise.
* dwarf-index-cache.c (debug_index_cache): Likewise.
* dwarf2-frame.c (dwarf2_frame_unwinders_enabled_p): Likewise.
* dwarf2-frame.h (dwarf2_frame_unwinders_enabled_p): Likewise.
* dwarf2read.c (check_physname): Likewise.
(use_deprecated_index_sections): Likewise.
(dwarf_always_disassemble): Likewise.
* eval.c (overload_resolution): Likewise.
* event-top.c (set_editing_cmd_var): Likewise.
(exec_done_display_p): Likewise.
* event-top.h (set_editing_cmd_var): Likewise.
(exec_done_display_p): Likewise.
* exec.c (write_files): Likewise.
* fbsd-nat.c (debug_fbsd_lwp): Likewise
(debug_fbsd_nat): Likewise.
* frame.h (struct frame_print_options) <print_raw_frame_arguments>:
Likewise.
(struct set_backtrace_options) <backtrace_past_main>: Likewise.
<backtrace_past_entry> Likewise.
* gdb-demangle.h (demangle): Likewise.
(asm_demangle): Likewise.
* gdb_bfd.c (bfd_sharing): Likewise.
* gdbcore.h (write_files): Likewise.
* gdbsupport/common-debug.c (show_debug_regs): Likewise.
* gdbsupport/common-debug.h (show_debug_regs): Likewise.
* gdbthread.h (print_thread_events): Likewise.
* gdbtypes.c (opaque_type_resolution): Likewise.
(strict_type_checking): Likewise.
* gnu-nat.c (gnu_debug_flag): Likewise.
* guile/scm-auto-load.c (auto_load_guile_scripts): Likewise.
* guile/scm-param.c (pascm_variable): Add boolval.
(add_setshow_generic): Update.
(pascm_param_value): Update.
(pascm_set_param_value_x): Update.
* hppa-tdep.c (hppa_debug): Change to bool..
* infcall.c (may_call_functions_p): Likewise.
(coerce_float_to_double_p): Likewise.
(unwind_on_signal_p): Likewise.
(unwind_on_terminating_exception_p): Likewise.
* infcmd.c (startup_with_shell): Likewise.
* inferior.c (print_inferior_events): Likewise.
* inferior.h (startup_with_shell): Likewise.
(print_inferior_events): Likewise.
* infrun.c (step_stop_if_no_debug): Likewise.
(detach_fork): Likewise.
(debug_displaced): Likewise.
(disable_randomization): Likewise.
(non_stop): Likewise.
(non_stop_1): Likewise.
(observer_mode): Likewise.
(observer_mode_1): Likewise.
(set_observer_mode): Update.
(sched_multi): Change to bool.
* infrun.h (debug_displaced): Likewise.
(sched_multi): Likewise.
(step_stop_if_no_debug): Likewise.
(non_stop): Likewise.
(disable_randomization): Likewise.
* linux-tdep.c (use_coredump_filter): Likewise.
(dump_excluded_mappings): Likewise.
* linux-thread-db.c (auto_load_thread_db): Likewise.
(check_thread_db_on_load): Likewise.
* main.c (captured_main_1): Update.
* maint-test-options.c (struct test_options_opts) <flag_opt, xx1_opt,
xx2_opt, boolean_opt>: Change to bool.
* maint-test-settings.c (maintenance_test_settings_boolean): Likewise.
* maint.c (maintenance_profile_p): Likewise.
(per_command_time): Likewise.
(per_command_space): Likewise.
(per_command_symtab): Likewise.
* memattr.c (inaccessible_by_default): Likewise.
* mi/mi-main.c (mi_async): Likewise.
(mi_async_1): Likewise.
* mips-tdep.c (mips64_transfers_32bit_regs_p): Likewise.
* nat/fork-inferior.h (startup_with_shell): Likewise.
* nat/linux-namespaces.c (debug_linux_namespaces): Likewise.
* nat/linux-namespaces.h (debug_linux_namespaces): Likewise.
* nios2-tdep.c (nios2_debug): Likewise.
* or1k-tdep.c (or1k_debug): Likewise.
* parse.c (parser_debug): Likewise.
* parser-defs.h (parser_debug): Likewise.
* printcmd.c (print_symbol_filename): Likewise.
* proc-api.c (procfs_trace): Likewise.
* python/py-auto-load.c (auto_load_python_scripts): Likewise.
* python/py-param.c (union parmpy_variable): Add "bool boolval" field.
(set_parameter_value): Update.
(add_setshow_generic): Update.
* python/py-value.c (copy_py_bool_obj): Change argument from int*
to bool*.
* python/python.c (gdbpy_parameter_value): Cast to bool* instead of
int*.
* ravenscar-thread.c (ravenscar_task_support): Change to bool.
* record-btrace.c (record_btrace_target::store_registers): Update.
* record-full.c (record_full_memory_query): Change to bool.
(record_full_stop_at_limit): Likewise.
* record-full.h (record_full_memory_query): Likewise.
* remote-notif.c (notif_debug): Likewise.
* remote-notif.h (notif_debug): Likewise.
* remote.c (use_range_stepping): Likewise.
(interrupt_on_connect): Likewise.
(remote_break): Likewise.
* ser-tcp.c (tcp_auto_retry): Likewise.
* ser-unix.c (serial_hwflow): Likewise.
* skip.c (debug_skip): Likewise.
* solib-aix.c (solib_aix_debug): Likewise.
* spu-tdep.c (spu_stop_on_load_p): Likewise.
(spu_auto_flush_cache_p): Likewise.
* stack.c (struct backtrace_cmd_options) <full, no_filters, hide>:
Likewise.
(struct info_print_options) <quiet>: Likewise.
* symfile-debug.c (debug_symfile): Likewise.
* symfile.c (auto_solib_add): Likewise.
(separate_debug_file_debug): Likewise.
* symfile.h (auto_solib_add): Likewise.
(separate_debug_file_debug): Likewise.
* symtab.c (basenames_may_differ): Likewise.
(struct filename_partial_match_opts) <dirname, basename>: Likewise.
(struct info_print_options) <quiet, exclude_minsyms>: Likewise.
(struct info_types_options) <quiet>: Likewise.
* symtab.h (demangle): Likewise.
(basenames_may_differ): Likewise.
* target-dcache.c (stack_cache_enabled_1): Likewise.
(code_cache_enabled_1): Likewise.
* target.c (trust_readonly): Likewise.
(may_write_registers): Likewise.
(may_write_memory): Likewise.
(may_insert_breakpoints): Likewise.
(may_insert_tracepoints): Likewise.
(may_insert_fast_tracepoints): Likewise.
(may_stop): Likewise.
(auto_connect_native_target): Likewise.
(target_stop_and_wait): Update.
(target_async_permitted): Change to bool.
(target_async_permitted_1): Likewise.
(may_write_registers_1): Likewise.
(may_write_memory_1): Likewise.
(may_insert_breakpoints_1): Likewise.
(may_insert_tracepoints_1): Likewise.
(may_insert_fast_tracepoints_1): Likewise.
(may_stop_1): Likewise.
* target.h (target_async_permitted): Likewise.
(may_write_registers): Likewise.
(may_write_memory): Likewise.
(may_insert_breakpoints): Likewise.
(may_insert_tracepoints): Likewise.
(may_insert_fast_tracepoints): Likewise.
(may_stop): Likewise.
* thread.c (struct info_threads_opts) <show_global_ids>: Likewise.
(make_thread_apply_all_options_def_group): Change argument from int*
to bool*.
(thread_apply_all_command): Update.
(print_thread_events): Change to bool.
* top.c (confirm): Likewise.
(command_editing_p): Likewise.
(history_expansion_p): Likewise.
(write_history_p): Likewise.
(info_verbose): Likewise.
* top.h (confirm): Likewise.
(history_expansion_p): Likewise.
* tracepoint.c (disconnected_tracing): Likewise.
(circular_trace_buffer): Likewise.
* typeprint.c (print_methods): Likewise.
(print_typedefs): Likewise.
* utils.c (debug_timestamp): Likewise.
(sevenbit_strings): Likewise.
(pagination_enabled): Likewise.
* utils.h (sevenbit_strings): Likewise.
(pagination_enabled): Likewise.
* valops.c (overload_resolution): Likewise.
* valprint.h (struct value_print_options) <prettyformat_arrays,
prettyformat_structs, vtblprint, unionprint, addressprint, objectprint,
stop_print_at_null, print_array_indexes, deref_ref, static_field_print,
pascal_static_field_print, raw, summary, symbol_print, finish_print>:
Likewise.
* windows-nat.c (new_console): Likewise.
(cygwin_exceptions): Likewise.
(new_group): Likewise.
(debug_exec): Likewise.
(debug_events): Likewise.
(debug_memory): Likewise.
(debug_exceptions): Likewise.
(useshell): Likewise.
* windows-tdep.c (maint_display_all_tib): Likewise.
* xml-support.c (debug_xml): Likewise.
2019-09-14 15:36:58 -04:00
|
|
|
static bool csky_debug = false;
|
2018-07-25 10:43:22 +01:00
|
|
|
|
2022-03-31 16:32:50 +01:00
|
|
|
static const reggroup *cr_reggroup;
|
|
|
|
|
static const reggroup *fr_reggroup;
|
|
|
|
|
static const reggroup *vr_reggroup;
|
|
|
|
|
static const reggroup *mmu_reggroup;
|
|
|
|
|
static const reggroup *prof_reggroup;
|
2018-07-25 10:43:22 +01:00
|
|
|
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
static const char *csky_supported_tdesc_feature_names[] = {
|
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|
|
(const char *)"org.gnu.csky.abiv2.gpr",
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(const char *)"org.gnu.csky.abiv2.fpu",
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(const char *)"org.gnu.csky.abiv2.cr",
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(const char *)"org.gnu.csky.abiv2.fvcr",
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(const char *)"org.gnu.csky.abiv2.mmu",
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(const char *)"org.gnu.csky.abiv2.tee",
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(const char *)"org.gnu.csky.abiv2.fpu2",
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(const char *)"org.gnu.csky.abiv2.bank0",
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(const char *)"org.gnu.csky.abiv2.bank1",
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(const char *)"org.gnu.csky.abiv2.bank2",
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(const char *)"org.gnu.csky.abiv2.bank3",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank4",
|
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|
|
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(const char *)"org.gnu.csky.abiv2.bank5",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank6",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank7",
|
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(const char *)"org.gnu.csky.abiv2.bank8",
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(const char *)"org.gnu.csky.abiv2.bank9",
|
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(const char *)"org.gnu.csky.abiv2.bank10",
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(const char *)"org.gnu.csky.abiv2.bank11",
|
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(const char *)"org.gnu.csky.abiv2.bank12",
|
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(const char *)"org.gnu.csky.abiv2.bank13",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank14",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank15",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank16",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank17",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank18",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank19",
|
|
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|
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(const char *)"org.gnu.csky.abiv2.bank20",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank21",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank22",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank23",
|
|
|
|
|
(const char *)"org.gnu.csky.abiv2.bank24",
|
|
|
|
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(const char *)"org.gnu.csky.abiv2.bank25",
|
|
|
|
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(const char *)"org.gnu.csky.abiv2.bank26",
|
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|
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(const char *)"org.gnu.csky.abiv2.bank27",
|
|
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|
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(const char *)"org.gnu.csky.abiv2.bank28",
|
|
|
|
|
(const char *)"org.gnu.csky.abiv2.bank29",
|
|
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|
|
(const char *)"org.gnu.csky.abiv2.bank30",
|
|
|
|
|
(const char *)"org.gnu.csky.abiv2.bank31"
|
|
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|
|
};
|
|
|
|
|
|
|
|
|
|
struct csky_supported_tdesc_register
|
|
|
|
|
{
|
|
|
|
|
char name[16];
|
|
|
|
|
int num;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct csky_supported_tdesc_register csky_supported_gpr_regs[] = {
|
|
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|
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{"r0", 0},
|
|
|
|
|
{"r1", 1},
|
|
|
|
|
{"r2", 2},
|
|
|
|
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{"r3", 3},
|
|
|
|
|
{"r4", 4},
|
|
|
|
|
{"r5", 5},
|
|
|
|
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{"r6", 6},
|
|
|
|
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{"r7", 7},
|
|
|
|
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{"r8", 8},
|
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{"r9", 9},
|
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|
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{"r10", 10},
|
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{"r11", 11},
|
|
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{"r12", 12},
|
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{"r13", 13},
|
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{"r14", 14},
|
|
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|
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{"r15", 15},
|
|
|
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{"r16", 16},
|
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|
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{"r17", 17},
|
|
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|
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{"r18", 18},
|
|
|
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{"r19", 19},
|
|
|
|
|
{"r20", 20},
|
|
|
|
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{"r21", 21},
|
|
|
|
|
{"r22", 22},
|
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|
|
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{"r23", 23},
|
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{"r24", 24},
|
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{"r25", 25},
|
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{"r26", 26},
|
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{"r27", 27},
|
|
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{"r28", 28},
|
|
|
|
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{"r28", 28},
|
|
|
|
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{"r29", 29},
|
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{"r30", 30},
|
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|
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{"r31", 31},
|
|
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|
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{"hi", CSKY_HI_REGNUM},
|
|
|
|
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{"lo", CSKY_LO_REGNUM},
|
|
|
|
|
{"pc", CSKY_PC_REGNUM}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct csky_supported_tdesc_register csky_supported_fpu_regs[] = {
|
|
|
|
|
/* fr0~fr15. */
|
|
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|
|
{"fr0", CSKY_FR0_REGNUM + 0},
|
|
|
|
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{"fr1", CSKY_FR0_REGNUM + 1},
|
|
|
|
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{"fr2", CSKY_FR0_REGNUM + 2},
|
|
|
|
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{"fr3", CSKY_FR0_REGNUM + 3},
|
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|
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{"fr4", CSKY_FR0_REGNUM + 4},
|
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{"fr5", CSKY_FR0_REGNUM + 5},
|
|
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|
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{"fr6", CSKY_FR0_REGNUM + 6},
|
|
|
|
|
{"fr7", CSKY_FR0_REGNUM + 7},
|
|
|
|
|
{"fr8", CSKY_FR0_REGNUM + 8},
|
|
|
|
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{"fr9", CSKY_FR0_REGNUM + 9},
|
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|
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{"fr10", CSKY_FR0_REGNUM + 10},
|
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|
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{"fr11", CSKY_FR0_REGNUM + 11},
|
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{"fr12", CSKY_FR0_REGNUM + 12},
|
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{"fr13", CSKY_FR0_REGNUM + 13},
|
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{"fr14", CSKY_FR0_REGNUM + 14},
|
|
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|
|
{"fr15", CSKY_FR0_REGNUM + 15},
|
|
|
|
|
/* fr16~fr31. */
|
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{"fr16", CSKY_FR16_REGNUM + 0},
|
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|
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{"fr17", CSKY_FR16_REGNUM + 1},
|
|
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|
|
{"fr18", CSKY_FR16_REGNUM + 2},
|
|
|
|
|
{"fr19", CSKY_FR16_REGNUM + 3},
|
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|
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{"fr20", CSKY_FR16_REGNUM + 4},
|
|
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|
|
{"fr21", CSKY_FR16_REGNUM + 5},
|
|
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|
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{"fr22", CSKY_FR16_REGNUM + 6},
|
|
|
|
|
{"fr23", CSKY_FR16_REGNUM + 7},
|
|
|
|
|
{"fr24", CSKY_FR16_REGNUM + 8},
|
|
|
|
|
{"fr25", CSKY_FR16_REGNUM + 9},
|
|
|
|
|
{"fr26", CSKY_FR16_REGNUM + 10},
|
|
|
|
|
{"fr27", CSKY_FR16_REGNUM + 11},
|
|
|
|
|
{"fr28", CSKY_FR16_REGNUM + 12},
|
|
|
|
|
{"fr29", CSKY_FR16_REGNUM + 13},
|
|
|
|
|
{"fr30", CSKY_FR16_REGNUM + 14},
|
|
|
|
|
{"fr31", CSKY_FR16_REGNUM + 15},
|
|
|
|
|
/* vr0~vr15. */
|
|
|
|
|
{"vr0", CSKY_VR0_REGNUM + 0},
|
|
|
|
|
{"vr1", CSKY_VR0_REGNUM + 1},
|
|
|
|
|
{"vr2", CSKY_VR0_REGNUM + 2},
|
|
|
|
|
{"vr3", CSKY_VR0_REGNUM + 3},
|
|
|
|
|
{"vr4", CSKY_VR0_REGNUM + 4},
|
|
|
|
|
{"vr5", CSKY_VR0_REGNUM + 5},
|
|
|
|
|
{"vr6", CSKY_VR0_REGNUM + 6},
|
|
|
|
|
{"vr7", CSKY_VR0_REGNUM + 7},
|
|
|
|
|
{"vr8", CSKY_VR0_REGNUM + 8},
|
|
|
|
|
{"vr9", CSKY_VR0_REGNUM + 9},
|
|
|
|
|
{"vr10", CSKY_VR0_REGNUM + 10},
|
|
|
|
|
{"vr11", CSKY_VR0_REGNUM + 11},
|
|
|
|
|
{"vr12", CSKY_VR0_REGNUM + 12},
|
|
|
|
|
{"vr13", CSKY_VR0_REGNUM + 13},
|
|
|
|
|
{"vr14", CSKY_VR0_REGNUM + 14},
|
|
|
|
|
{"vr15", CSKY_VR0_REGNUM + 15},
|
|
|
|
|
/* fpu control registers. */
|
|
|
|
|
{"fcr", CSKY_FCR_REGNUM + 0},
|
|
|
|
|
{"fid", CSKY_FCR_REGNUM + 1},
|
|
|
|
|
{"fesr", CSKY_FCR_REGNUM + 2},
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct csky_supported_tdesc_register csky_supported_ar_regs[] = {
|
|
|
|
|
{"ar0", CSKY_AR0_REGNUM + 0},
|
|
|
|
|
{"ar1", CSKY_AR0_REGNUM + 1},
|
|
|
|
|
{"ar2", CSKY_AR0_REGNUM + 2},
|
|
|
|
|
{"ar3", CSKY_AR0_REGNUM + 3},
|
|
|
|
|
{"ar4", CSKY_AR0_REGNUM + 4},
|
|
|
|
|
{"ar5", CSKY_AR0_REGNUM + 5},
|
|
|
|
|
{"ar6", CSKY_AR0_REGNUM + 6},
|
|
|
|
|
{"ar7", CSKY_AR0_REGNUM + 7},
|
|
|
|
|
{"ar8", CSKY_AR0_REGNUM + 8},
|
|
|
|
|
{"ar9", CSKY_AR0_REGNUM + 9},
|
|
|
|
|
{"ar10", CSKY_AR0_REGNUM + 10},
|
|
|
|
|
{"ar11", CSKY_AR0_REGNUM + 11},
|
|
|
|
|
{"ar12", CSKY_AR0_REGNUM + 12},
|
|
|
|
|
{"ar13", CSKY_AR0_REGNUM + 13},
|
|
|
|
|
{"ar14", CSKY_AR0_REGNUM + 14},
|
|
|
|
|
{"ar15", CSKY_AR0_REGNUM + 15},
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct csky_supported_tdesc_register csky_supported_bank0_regs[] = {
|
|
|
|
|
{"cr0", CSKY_CR0_REGNUM + 0},
|
|
|
|
|
{"cr1", CSKY_CR0_REGNUM + 1},
|
|
|
|
|
{"cr2", CSKY_CR0_REGNUM + 2},
|
|
|
|
|
{"cr3", CSKY_CR0_REGNUM + 3},
|
|
|
|
|
{"cr4", CSKY_CR0_REGNUM + 4},
|
|
|
|
|
{"cr5", CSKY_CR0_REGNUM + 5},
|
|
|
|
|
{"cr6", CSKY_CR0_REGNUM + 6},
|
|
|
|
|
{"cr7", CSKY_CR0_REGNUM + 7},
|
|
|
|
|
{"cr8", CSKY_CR0_REGNUM + 8},
|
|
|
|
|
{"cr9", CSKY_CR0_REGNUM + 9},
|
|
|
|
|
{"cr10", CSKY_CR0_REGNUM + 10},
|
|
|
|
|
{"cr11", CSKY_CR0_REGNUM + 11},
|
|
|
|
|
{"cr12", CSKY_CR0_REGNUM + 12},
|
|
|
|
|
{"cr13", CSKY_CR0_REGNUM + 13},
|
|
|
|
|
{"cr14", CSKY_CR0_REGNUM + 14},
|
|
|
|
|
{"cr15", CSKY_CR0_REGNUM + 15},
|
|
|
|
|
{"cr16", CSKY_CR0_REGNUM + 16},
|
|
|
|
|
{"cr17", CSKY_CR0_REGNUM + 17},
|
|
|
|
|
{"cr18", CSKY_CR0_REGNUM + 18},
|
|
|
|
|
{"cr19", CSKY_CR0_REGNUM + 19},
|
|
|
|
|
{"cr20", CSKY_CR0_REGNUM + 20},
|
|
|
|
|
{"cr21", CSKY_CR0_REGNUM + 21},
|
|
|
|
|
{"cr22", CSKY_CR0_REGNUM + 22},
|
|
|
|
|
{"cr23", CSKY_CR0_REGNUM + 23},
|
|
|
|
|
{"cr24", CSKY_CR0_REGNUM + 24},
|
|
|
|
|
{"cr25", CSKY_CR0_REGNUM + 25},
|
|
|
|
|
{"cr26", CSKY_CR0_REGNUM + 26},
|
|
|
|
|
{"cr27", CSKY_CR0_REGNUM + 27},
|
|
|
|
|
{"cr28", CSKY_CR0_REGNUM + 28},
|
|
|
|
|
{"cr29", CSKY_CR0_REGNUM + 29},
|
|
|
|
|
{"cr30", CSKY_CR0_REGNUM + 30},
|
|
|
|
|
{"cr31", CSKY_CR0_REGNUM + 31}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct csky_supported_tdesc_register csky_supported_mmu_regs[] = {
|
|
|
|
|
{"mcr0", 128},
|
|
|
|
|
{"mcr2", 129},
|
|
|
|
|
{"mcr3", 130},
|
|
|
|
|
{"mcr4", 131},
|
|
|
|
|
{"mcr6", 132},
|
|
|
|
|
{"mcr8", 133},
|
|
|
|
|
{"mcr29", 134},
|
|
|
|
|
{"mcr30", 135},
|
|
|
|
|
{"mcr31", 136}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct csky_supported_tdesc_register csky_supported_bank15_regs[] = {
|
|
|
|
|
{"cp15cp1", 253},
|
|
|
|
|
{"cp15cp5", 254},
|
|
|
|
|
{"cp15cp7", 255},
|
|
|
|
|
{"cp15cp9", 256},
|
|
|
|
|
{"cp15cp10", 257},
|
|
|
|
|
{"cp15cp11", 258},
|
|
|
|
|
{"cp15cp12", 259},
|
|
|
|
|
{"cp15cp13", 260},
|
|
|
|
|
{"cp15cp14", 261},
|
|
|
|
|
{"cp15cp15", 262},
|
|
|
|
|
{"cp15cp16", 263},
|
|
|
|
|
{"cp15cp17", 264},
|
|
|
|
|
{"cp15cp18", 265},
|
|
|
|
|
{"cp15cp19", 266},
|
|
|
|
|
{"cp15cp20", 267},
|
|
|
|
|
{"cp15cp21", 268},
|
|
|
|
|
{"cp15cp22", 269},
|
|
|
|
|
{"cp15cp23", 270},
|
|
|
|
|
{"cp15cp24", 271},
|
|
|
|
|
{"cp15cp25", 272},
|
|
|
|
|
{"cp15cp26", 273},
|
|
|
|
|
{"cp15cp27", 274},
|
|
|
|
|
{"cp15cp28", 275},
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct csky_supported_tdesc_register csky_supported_alias_regs[] = {
|
|
|
|
|
/* Alias register names for Bank0. */
|
|
|
|
|
{"psr", CSKY_CR0_REGNUM + 0},
|
|
|
|
|
{"vbr", CSKY_CR0_REGNUM + 1},
|
|
|
|
|
{"epsr", CSKY_CR0_REGNUM + 2},
|
|
|
|
|
{"fpsr", CSKY_CR0_REGNUM + 3},
|
|
|
|
|
{"epc", CSKY_CR0_REGNUM + 4},
|
|
|
|
|
{"fpc", CSKY_CR0_REGNUM + 5},
|
|
|
|
|
{"ss0", CSKY_CR0_REGNUM + 6},
|
|
|
|
|
{"ss1", CSKY_CR0_REGNUM + 7},
|
|
|
|
|
{"ss2", CSKY_CR0_REGNUM + 8},
|
|
|
|
|
{"ss3", CSKY_CR0_REGNUM + 9},
|
|
|
|
|
{"ss4", CSKY_CR0_REGNUM + 10},
|
|
|
|
|
{"gcr", CSKY_CR0_REGNUM + 11},
|
|
|
|
|
{"gsr", CSKY_CR0_REGNUM + 12},
|
|
|
|
|
{"cpuid", CSKY_CR0_REGNUM + 13},
|
|
|
|
|
{"ccr", CSKY_CR0_REGNUM + 18},
|
|
|
|
|
{"capr", CSKY_CR0_REGNUM + 19},
|
|
|
|
|
{"pacr", CSKY_CR0_REGNUM + 20},
|
|
|
|
|
{"prsr", CSKY_CR0_REGNUM + 21},
|
|
|
|
|
{"chr", CSKY_CR0_REGNUM + 31},
|
|
|
|
|
/* Alias register names for MMU. */
|
|
|
|
|
{"mir", 128},
|
|
|
|
|
{"mel0", 129},
|
|
|
|
|
{"mel1", 130},
|
|
|
|
|
{"meh", 131},
|
|
|
|
|
{"mpr", 132},
|
|
|
|
|
{"mcir", 133},
|
|
|
|
|
{"mpgd", 134},
|
|
|
|
|
{"msa0", 135},
|
|
|
|
|
{"msa1", 136},
|
|
|
|
|
/* Alias register names for Bank1. */
|
|
|
|
|
{"ebr", 190},
|
|
|
|
|
{"errlc", 195},
|
|
|
|
|
{"erraddr", 196},
|
|
|
|
|
{"errsts", 197},
|
|
|
|
|
{"errinj", 198},
|
|
|
|
|
{"usp", 203},
|
|
|
|
|
{"int_sp", 204},
|
|
|
|
|
{"itcmcr", 211},
|
|
|
|
|
{"dtcmcr", 212},
|
|
|
|
|
{"cindex", 215},
|
|
|
|
|
{"cdata0", 216},
|
|
|
|
|
{"cdata1", 217},
|
|
|
|
|
{"cdata2", 218},
|
|
|
|
|
{"cins", 220},
|
|
|
|
|
/* Alias register names for Bank3. */
|
|
|
|
|
{"sepsr", 221},
|
|
|
|
|
{"t_wssr", 221},
|
|
|
|
|
{"sevbr", 222},
|
|
|
|
|
{"t_wrcr", 222},
|
|
|
|
|
{"seepsr", 223},
|
|
|
|
|
{"seepc", 225},
|
|
|
|
|
{"nsssp", 227},
|
|
|
|
|
{"t_usp", 228},
|
|
|
|
|
{"dcr", 229},
|
|
|
|
|
{"t_pcr", 230},
|
|
|
|
|
};
|
|
|
|
|
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
/* Functions declaration. */
|
|
|
|
|
|
|
|
|
|
static const char *
|
|
|
|
|
csky_pseudo_register_name (struct gdbarch *gdbarch, int regno);
|
|
|
|
|
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
/* Get csky supported registers's count for tdesc xml. */
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
static int
|
|
|
|
|
csky_get_supported_tdesc_registers_count()
|
|
|
|
|
{
|
|
|
|
|
int count = 0;
|
|
|
|
|
count += ARRAY_SIZE (csky_supported_gpr_regs);
|
|
|
|
|
count += ARRAY_SIZE (csky_supported_fpu_regs);
|
|
|
|
|
count += ARRAY_SIZE (csky_supported_ar_regs);
|
|
|
|
|
count += ARRAY_SIZE (csky_supported_bank0_regs);
|
|
|
|
|
count += ARRAY_SIZE (csky_supported_mmu_regs);
|
|
|
|
|
count += ARRAY_SIZE (csky_supported_bank15_regs);
|
|
|
|
|
count += ARRAY_SIZE (csky_supported_alias_regs);
|
|
|
|
|
/* Bank1~Bank14, Bank16~Bank31. */
|
|
|
|
|
count += 32 * (14 + 16);
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return a supported register according to index. */
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
static const struct csky_supported_tdesc_register *
|
|
|
|
|
csky_get_supported_register_by_index (int index)
|
|
|
|
|
{
|
|
|
|
|
static struct csky_supported_tdesc_register tdesc_reg;
|
|
|
|
|
int count = 0;
|
|
|
|
|
int multi, remain;
|
|
|
|
|
int count_gpr = ARRAY_SIZE (csky_supported_gpr_regs);
|
|
|
|
|
int count_fpu = ARRAY_SIZE (csky_supported_fpu_regs);
|
|
|
|
|
int count_ar = ARRAY_SIZE (csky_supported_ar_regs);
|
|
|
|
|
int count_bank0 = ARRAY_SIZE (csky_supported_bank0_regs);
|
|
|
|
|
int count_mmu = ARRAY_SIZE (csky_supported_mmu_regs);
|
|
|
|
|
int count_bank15 = ARRAY_SIZE (csky_supported_bank15_regs);
|
|
|
|
|
int count_alias = ARRAY_SIZE (csky_supported_alias_regs);
|
|
|
|
|
|
|
|
|
|
count = count_gpr;
|
|
|
|
|
if (index < count)
|
|
|
|
|
return &csky_supported_gpr_regs[index];
|
|
|
|
|
if (index < (count + count_fpu))
|
|
|
|
|
return &csky_supported_fpu_regs[index - count];
|
|
|
|
|
count += count_fpu;
|
|
|
|
|
if (index < (count + count_ar))
|
|
|
|
|
return &csky_supported_ar_regs[index - count];
|
|
|
|
|
count += count_ar;
|
|
|
|
|
if (index < (count + count_bank0))
|
|
|
|
|
return &csky_supported_bank0_regs[index - count];
|
|
|
|
|
count += count_bank0;
|
|
|
|
|
if (index < (count + count_mmu))
|
|
|
|
|
return &csky_supported_mmu_regs[index - count];
|
|
|
|
|
count += count_mmu;
|
|
|
|
|
if (index < (count + count_bank15))
|
|
|
|
|
return &csky_supported_bank15_regs[index - count];
|
|
|
|
|
count += count_bank15;
|
|
|
|
|
if (index < (count + count_alias))
|
|
|
|
|
return &csky_supported_alias_regs[index - count];
|
|
|
|
|
count += count_alias;
|
|
|
|
|
index -= count;
|
|
|
|
|
multi = index / 32;
|
|
|
|
|
remain = index % 32;
|
|
|
|
|
switch (multi)
|
|
|
|
|
{
|
|
|
|
|
case 0: /* Bank1. */
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
sprintf (tdesc_reg.name, "cp1cr%d", remain);
|
|
|
|
|
tdesc_reg.num = 189 + remain;
|
|
|
|
|
}
|
|
|
|
|
break;
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
case 1: /* Bank2. */
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
sprintf (tdesc_reg.name, "cp2cr%d", remain);
|
|
|
|
|
tdesc_reg.num = 276 + remain;
|
|
|
|
|
}
|
|
|
|
|
break;
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
case 2: /* Bank3. */
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
sprintf (tdesc_reg.name, "cp3cr%d", remain);
|
|
|
|
|
tdesc_reg.num = 221 + remain;
|
|
|
|
|
}
|
|
|
|
|
break;
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
case 3: /* Bank4. */
|
|
|
|
|
case 4: /* Bank5. */
|
|
|
|
|
case 5: /* Bank6. */
|
|
|
|
|
case 6: /* Bank7. */
|
|
|
|
|
case 7: /* Bank8. */
|
|
|
|
|
case 8: /* Bank9. */
|
|
|
|
|
case 9: /* Bank10. */
|
|
|
|
|
case 10: /* Bank11. */
|
|
|
|
|
case 11: /* Bank12. */
|
|
|
|
|
case 12: /* Bank13. */
|
|
|
|
|
case 13: /* Bank14. */
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
/* Regitsers in Bank4~14 have continuous regno with start 308. */
|
|
|
|
|
sprintf (tdesc_reg.name, "cp%dcr%d", (multi + 1), remain);
|
|
|
|
|
tdesc_reg.num = 308 + ((multi - 3) * 32) + remain;
|
|
|
|
|
}
|
|
|
|
|
break;
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
case 14: /* Bank16. */
|
|
|
|
|
case 15: /* Bank17. */
|
|
|
|
|
case 16: /* Bank18. */
|
|
|
|
|
case 17: /* Bank19. */
|
|
|
|
|
case 18: /* Bank20. */
|
|
|
|
|
case 19: /* Bank21. */
|
|
|
|
|
case 20: /* Bank22. */
|
|
|
|
|
case 21: /* Bank23. */
|
|
|
|
|
case 22: /* Bank24. */
|
|
|
|
|
case 23: /* Bank25. */
|
|
|
|
|
case 24: /* Bank26. */
|
|
|
|
|
case 25: /* Bank27. */
|
|
|
|
|
case 26: /* Bank28. */
|
|
|
|
|
case 27: /* Bank29. */
|
|
|
|
|
case 28: /* Bank30. */
|
|
|
|
|
case 29: /* Bank31. */
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
/* Regitsers in Bank16~31 have continuous regno with start 660. */
|
|
|
|
|
sprintf (tdesc_reg.name, "cp%dcr%d", (multi + 2), remain);
|
|
|
|
|
tdesc_reg.num = 660 + ((multi - 14) * 32) + remain;
|
|
|
|
|
}
|
|
|
|
|
break;
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
default:
|
2023-03-09 14:56:09 -05:00
|
|
|
return NULL;
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
}
|
|
|
|
|
return &tdesc_reg;
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-25 10:43:22 +01:00
|
|
|
/* Convenience function to print debug messages in prologue analysis. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_savedreg_msg (int regno, int offsets[], bool print_continuing)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog, "csky: r%d saved at offset 0x%x\n",
|
|
|
|
|
regno, offsets[regno]);
|
2018-07-25 10:43:22 +01:00
|
|
|
if (print_continuing)
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog, "csky: continuing\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Check whether the instruction at ADDR is 16-bit or not. */
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
csky_pc_is_csky16 (struct gdbarch *gdbarch, CORE_ADDR addr)
|
|
|
|
|
{
|
|
|
|
|
gdb_byte target_mem[2];
|
|
|
|
|
int status;
|
|
|
|
|
unsigned int insn;
|
|
|
|
|
int ret = 1;
|
|
|
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
|
|
|
|
|
|
|
|
|
status = target_read_memory (addr, target_mem, 2);
|
|
|
|
|
/* Assume a 16-bit instruction if we can't read memory. */
|
|
|
|
|
if (status)
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
/* Get instruction from memory. */
|
|
|
|
|
insn = extract_unsigned_integer (target_mem, 2, byte_order);
|
|
|
|
|
if ((insn & CSKY_32_INSN_MASK) == CSKY_32_INSN_MASK)
|
|
|
|
|
ret = 0;
|
|
|
|
|
else if (insn == CSKY_BKPT_INSN)
|
|
|
|
|
{
|
|
|
|
|
/* Check for 32-bit bkpt instruction which is all 0. */
|
|
|
|
|
status = target_read_memory (addr + 2, target_mem, 2);
|
|
|
|
|
if (status)
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
insn = extract_unsigned_integer (target_mem, 2, byte_order);
|
|
|
|
|
if (insn == CSKY_BKPT_INSN)
|
|
|
|
|
ret = 0;
|
|
|
|
|
}
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Get one instruction at ADDR and store it in INSN. Return 2 for
|
|
|
|
|
a 16-bit instruction or 4 for a 32-bit instruction. */
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
csky_get_insn (struct gdbarch *gdbarch, CORE_ADDR addr, unsigned int *insn)
|
|
|
|
|
{
|
|
|
|
|
gdb_byte target_mem[2];
|
|
|
|
|
unsigned int insn_type;
|
|
|
|
|
int status;
|
|
|
|
|
int insn_len = 2;
|
|
|
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
|
|
|
|
|
|
|
|
|
status = target_read_memory (addr, target_mem, 2);
|
|
|
|
|
if (status)
|
|
|
|
|
memory_error (TARGET_XFER_E_IO, addr);
|
|
|
|
|
|
|
|
|
|
insn_type = extract_unsigned_integer (target_mem, 2, byte_order);
|
|
|
|
|
if (CSKY_32_INSN_MASK == (insn_type & CSKY_32_INSN_MASK))
|
|
|
|
|
{
|
|
|
|
|
status = target_read_memory (addr + 2, target_mem, 2);
|
|
|
|
|
if (status)
|
|
|
|
|
memory_error (TARGET_XFER_E_IO, addr);
|
|
|
|
|
insn_type = ((insn_type << 16)
|
|
|
|
|
| extract_unsigned_integer (target_mem, 2, byte_order));
|
|
|
|
|
insn_len = 4;
|
|
|
|
|
}
|
|
|
|
|
*insn = insn_type;
|
|
|
|
|
return insn_len;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implement the read_pc gdbarch method. */
|
|
|
|
|
|
|
|
|
|
static CORE_ADDR
|
|
|
|
|
csky_read_pc (readable_regcache *regcache)
|
|
|
|
|
{
|
|
|
|
|
ULONGEST pc;
|
|
|
|
|
regcache->cooked_read (CSKY_PC_REGNUM, &pc);
|
|
|
|
|
return pc;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implement the write_pc gdbarch method. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
csky_write_pc (regcache *regcache, CORE_ADDR val)
|
|
|
|
|
{
|
|
|
|
|
regcache_cooked_write_unsigned (regcache, CSKY_PC_REGNUM, val);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* C-Sky ABI register names. */
|
|
|
|
|
|
Apply 'const' in more places
Many global arrays in gdb could be marked "const" but are not. This
patch changes some of them. (There may be other arrays that could
benefit from this treatment. I only examined arrays of strings.)
This lets the linker move some symbols to the readonly data section.
For example, previously:
0000000000000000 d _ZL18can_use_agent_enum
is now:
0000000000000030 r _ZL18can_use_agent_enum
2020-09-14 Tom Tromey <tromey@adacore.com>
* x86-tdep.h (x86_in_indirect_branch_thunk): Update.
* x86-tdep.c (x86_is_thunk_register_name)
(x86_in_indirect_branch_thunk): Update.
* sparc64-tdep.c (sparc64_fpu_register_names)
(sparc64_cp0_register_names, sparc64_register_names)
(sparc64_pseudo_register_names): Now const.
* sparc-tdep.h (struct gdbarch_tdep) <fpu_register_names,
cp0_registers_num>: Now const.
* sparc-tdep.c (sparc_core_register_names)
(sparc32_fpu_register_names, sparc32_cp0_register_names)
(sparc32_pseudo_register_names): Now const.
(validate_tdesc_registers): Update.
* rust-lang.c (rust_extensions): Now const.
* p-lang.c (p_extensions): Now const.
* objc-lang.c (objc_extensions): Now const.
* nto-tdep.c (nto_thread_state_str): Now const.
* moxie-tdep.c (moxie_register_names): Now const.
* mips-tdep.h (struct gdbarch_tdep) <mips_processor_reg_names>:
Now const.
* mips-tdep.c (mips_generic_reg_names, mips_tx39_reg_names)
(mips_linux_reg_names): Now const.
(mips_gdbarch_init): Update.
* microblaze-tdep.c (microblaze_register_names): Now const.
* m68k-tdep.c (m68k_register_names): Now const.
* m32r-tdep.c (m32r_register_names): Now const.
* ia64-tdep.c (ia64_register_names): Now const.
* i386-tdep.h (struct gdbarch_tdep) <register_names,
ymmh_register_names, ymm16h_regnum, mpx_register_names,
k_register_names, zmmh_register_names, xmm_avx512_register_names,
ymm_avx512_register_names, pkeys_register_names>: Now const.
* i386-tdep.c (i386_register_names, i386_zmm_names)
(i386_zmmh_names, i386_k_names, i386_ymm_names, i386_ymmh_names)
(i386_mpx_names, i386_pkeys_names, i386_bnd_names)
(i386_mmx_names, i386_byte_names, i386_word_names): Now const.
* f-lang.c (f_extensions): Now const.
* d-lang.c (d_extensions): Now const.
* csky-tdep.c (csky_register_names): Now const.
* charset.c (default_charset_names, charset_enum): Now const.
(_initialize_charset): Update.
* c-lang.c (c_extensions, cplus_extensions, asm_extensions): Now
const.
* bsd-uthread.c (bsd_uthread_solib_names): Now const.
(bsd_uthread_solib_loaded): Update.
(bsd_uthread_state): Now const.
* amd64-tdep.c (amd64_register_names, amd64_ymm_names)
(amd64_ymm_avx512_names, amd64_ymmh_names)
(amd64_ymmh_avx512_names, amd64_mpx_names, amd64_k_names)
(amd64_zmmh_names, amd64_zmm_names, amd64_xmm_avx512_names)
(amd64_pkeys_names, amd64_byte_names, amd64_word_names)
(amd64_dword_names): Now const.
* agent.c (can_use_agent_enum): Now const.
* ada-tasks.c (task_states, long_task_states): Now const.
* ada-lang.c (known_runtime_file_name_patterns)
(known_auxiliary_function_name_patterns, attribute_names)
(standard_exc, ada_extensions): Now const.
gdbserver/ChangeLog
2020-09-14 Tom Tromey <tromey@adacore.com>
* tracepoint.cc (eval_result_names): Now const.
* ax.cc (gdb_agent_op_names): Now const.
2020-09-14 12:09:59 -06:00
|
|
|
static const char * const csky_register_names[] =
|
2018-07-25 10:43:22 +01:00
|
|
|
{
|
|
|
|
|
/* General registers 0 - 31. */
|
|
|
|
|
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
|
|
|
|
|
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
|
|
|
|
|
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
|
|
|
|
|
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
|
|
|
|
|
|
|
|
|
|
/* DSP hilo registers 36 and 37. */
|
|
|
|
|
"", "", "", "", "hi", "lo", "", "",
|
|
|
|
|
|
|
|
|
|
/* FPU/VPU general registers 40 - 71. */
|
|
|
|
|
"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
|
|
|
|
|
"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
|
|
|
|
|
"vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
|
|
|
|
|
"vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
|
|
|
|
|
|
|
|
|
|
/* Program counter 72. */
|
|
|
|
|
"pc",
|
|
|
|
|
|
|
|
|
|
/* Optional registers (ar) 73 - 88. */
|
|
|
|
|
"ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7",
|
|
|
|
|
"ar8", "ar9", "ar10", "ar11", "ar12", "ar13", "ar14", "ar15",
|
|
|
|
|
|
|
|
|
|
/* Control registers (cr) 89 - 119. */
|
|
|
|
|
"psr", "vbr", "epsr", "fpsr", "epc", "fpc", "ss0", "ss1",
|
|
|
|
|
"ss2", "ss3", "ss4", "gcr", "gsr", "cr13", "cr14", "cr15",
|
|
|
|
|
"cr16", "cr17", "cr18", "cr19", "cr20", "cr21", "cr22", "cr23",
|
|
|
|
|
"cr24", "cr25", "cr26", "cr27", "cr28", "cr29", "cr30", "cr31",
|
|
|
|
|
|
|
|
|
|
/* FPU/VPU control registers 121 ~ 123. */
|
|
|
|
|
/* User sp 127. */
|
|
|
|
|
"fid", "fcr", "fesr", "", "", "", "usp",
|
|
|
|
|
|
|
|
|
|
/* MMU control registers: 128 - 136. */
|
|
|
|
|
"mcr0", "mcr2", "mcr3", "mcr4", "mcr6", "mcr8", "mcr29", "mcr30",
|
|
|
|
|
"mcr31", "", "", "",
|
|
|
|
|
|
|
|
|
|
/* Profiling control registers 140 - 143. */
|
|
|
|
|
/* Profiling software general registers 144 - 157. */
|
|
|
|
|
"profcr0", "profcr1", "profcr2", "profcr3", "profsgr0", "profsgr1",
|
|
|
|
|
"profsgr2", "profsgr3", "profsgr4", "profsgr5", "profsgr6", "profsgr7",
|
|
|
|
|
"profsgr8", "profsgr9", "profsgr10","profsgr11","profsgr12", "profsgr13",
|
|
|
|
|
"", "",
|
|
|
|
|
|
|
|
|
|
/* Profiling architecture general registers 160 - 174. */
|
|
|
|
|
"profagr0", "profagr1", "profagr2", "profagr3", "profagr4", "profagr5",
|
|
|
|
|
"profagr6", "profagr7", "profagr8", "profagr9", "profagr10","profagr11",
|
|
|
|
|
"profagr12","profagr13","profagr14", "",
|
|
|
|
|
|
|
|
|
|
/* Profiling extension general registers 176 - 188. */
|
|
|
|
|
"profxgr0", "profxgr1", "profxgr2", "profxgr3", "profxgr4", "profxgr5",
|
|
|
|
|
"profxgr6", "profxgr7", "profxgr8", "profxgr9", "profxgr10","profxgr11",
|
|
|
|
|
"profxgr12",
|
|
|
|
|
|
|
|
|
|
/* Control registers in bank1. */
|
|
|
|
|
"", "", "", "", "", "", "", "",
|
|
|
|
|
"", "", "", "", "", "", "", "",
|
|
|
|
|
"cp1cr16", "cp1cr17", "cp1cr18", "cp1cr19", "cp1cr20", "", "", "",
|
|
|
|
|
"", "", "", "", "", "", "", "",
|
|
|
|
|
|
|
|
|
|
/* Control registers in bank3 (ICE). */
|
|
|
|
|
"sepsr", "sevbr", "seepsr", "", "seepc", "", "nsssp", "seusp",
|
|
|
|
|
"sedcr", "", "", "", "", "", "", "",
|
|
|
|
|
"", "", "", "", "", "", "", "",
|
|
|
|
|
"", "", "", "", "", "", "", ""
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Implement the register_name gdbarch method. */
|
|
|
|
|
|
|
|
|
|
static const char *
|
|
|
|
|
csky_register_name (struct gdbarch *gdbarch, int reg_nr)
|
|
|
|
|
{
|
2022-09-01 15:39:59 +01:00
|
|
|
if (reg_nr >= gdbarch_num_regs (gdbarch))
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
return csky_pseudo_register_name (gdbarch, reg_nr);
|
|
|
|
|
|
|
|
|
|
if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
|
|
|
|
|
return tdesc_register_name (gdbarch, reg_nr);
|
|
|
|
|
|
2018-07-25 10:43:22 +01:00
|
|
|
return csky_register_names[reg_nr];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Construct vector type for vrx registers. */
|
|
|
|
|
|
|
|
|
|
static struct type *
|
|
|
|
|
csky_vector_type (struct gdbarch *gdbarch)
|
|
|
|
|
{
|
|
|
|
|
const struct builtin_type *bt = builtin_type (gdbarch);
|
|
|
|
|
|
|
|
|
|
struct type *t;
|
|
|
|
|
|
|
|
|
|
t = arch_composite_type (gdbarch, "__gdb_builtin_type_vec128i",
|
|
|
|
|
TYPE_CODE_UNION);
|
|
|
|
|
|
|
|
|
|
append_composite_type_field (t, "u32",
|
|
|
|
|
init_vector_type (bt->builtin_int32, 4));
|
|
|
|
|
append_composite_type_field (t, "u16",
|
|
|
|
|
init_vector_type (bt->builtin_int16, 8));
|
|
|
|
|
append_composite_type_field (t, "u8",
|
|
|
|
|
init_vector_type (bt->builtin_int8, 16));
|
|
|
|
|
|
2020-09-14 11:08:02 -04:00
|
|
|
t->set_is_vector (true);
|
2020-05-16 12:15:54 -04:00
|
|
|
t->set_name ("builtin_type_vec128i");
|
2018-07-25 10:43:22 +01:00
|
|
|
|
|
|
|
|
return t;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return the GDB type object for the "standard" data type
|
|
|
|
|
of data in register N. */
|
|
|
|
|
|
|
|
|
|
static struct type *
|
|
|
|
|
csky_register_type (struct gdbarch *gdbarch, int reg_nr)
|
|
|
|
|
{
|
2022-11-09 19:41:02 +08:00
|
|
|
int num_regs = gdbarch_num_regs (gdbarch);
|
|
|
|
|
csky_gdbarch_tdep *tdep
|
|
|
|
|
= gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
|
|
|
|
|
|
|
|
|
|
if (tdep->fv_pseudo_registers_count)
|
|
|
|
|
{
|
|
|
|
|
if ((reg_nr >= num_regs)
|
|
|
|
|
&& (reg_nr < (num_regs + tdep->fv_pseudo_registers_count)))
|
|
|
|
|
return builtin_type (gdbarch)->builtin_int32;
|
|
|
|
|
}
|
|
|
|
|
|
2022-11-09 19:50:35 +08:00
|
|
|
/* Vector register has 128 bits, and only in ck810. Just return
|
|
|
|
|
csky_vector_type(), not check tdesc_has_registers(), is in case
|
2023-06-03 22:43:57 +02:00
|
|
|
of some GDB stub does not describe type for Vector registers
|
2022-11-09 19:50:35 +08:00
|
|
|
in the target-description-xml. */
|
|
|
|
|
if ((reg_nr >= CSKY_VR0_REGNUM) && (reg_nr <= CSKY_VR0_REGNUM + 15))
|
|
|
|
|
return csky_vector_type (gdbarch);
|
|
|
|
|
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
/* If type has been described in tdesc-xml, use it. */
|
|
|
|
|
if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
|
|
|
|
|
{
|
|
|
|
|
struct type *tdesc_t = tdesc_register_type (gdbarch, reg_nr);
|
|
|
|
|
if (tdesc_t)
|
2023-03-09 14:56:09 -05:00
|
|
|
return tdesc_t;
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
}
|
|
|
|
|
|
2018-07-25 10:43:22 +01:00
|
|
|
/* PC, EPC, FPC is a text pointer. */
|
|
|
|
|
if ((reg_nr == CSKY_PC_REGNUM) || (reg_nr == CSKY_EPC_REGNUM)
|
|
|
|
|
|| (reg_nr == CSKY_FPC_REGNUM))
|
|
|
|
|
return builtin_type (gdbarch)->builtin_func_ptr;
|
|
|
|
|
|
|
|
|
|
/* VBR is a data pointer. */
|
|
|
|
|
if (reg_nr == CSKY_VBR_REGNUM)
|
|
|
|
|
return builtin_type (gdbarch)->builtin_data_ptr;
|
|
|
|
|
|
|
|
|
|
/* Float register has 64 bits, and only in ck810. */
|
|
|
|
|
if ((reg_nr >=CSKY_FR0_REGNUM) && (reg_nr <= CSKY_FR0_REGNUM + 15))
|
2023-03-13 11:30:08 -06:00
|
|
|
{
|
|
|
|
|
type_allocator alloc (gdbarch);
|
|
|
|
|
return init_float_type (alloc, 64, "builtin_type_csky_ext",
|
2018-07-25 10:43:22 +01:00
|
|
|
floatformats_ieee_double);
|
2023-03-13 11:30:08 -06:00
|
|
|
}
|
2018-07-25 10:43:22 +01:00
|
|
|
|
|
|
|
|
/* Profiling general register has 48 bits, we use 64bit. */
|
|
|
|
|
if ((reg_nr >= CSKY_PROFGR_REGNUM) && (reg_nr <= CSKY_PROFGR_REGNUM + 44))
|
|
|
|
|
return builtin_type (gdbarch)->builtin_uint64;
|
|
|
|
|
|
|
|
|
|
if (reg_nr == CSKY_SP_REGNUM)
|
|
|
|
|
return builtin_type (gdbarch)->builtin_data_ptr;
|
|
|
|
|
|
|
|
|
|
/* Others are 32 bits. */
|
|
|
|
|
return builtin_type (gdbarch)->builtin_int32;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Data structure to marshall items in a dummy stack frame when
|
|
|
|
|
calling a function in the inferior. */
|
|
|
|
|
|
2022-05-18 09:49:35 -06:00
|
|
|
struct csky_stack_item
|
2018-07-25 10:43:22 +01:00
|
|
|
{
|
2022-05-18 09:49:35 -06:00
|
|
|
csky_stack_item (int len_, const gdb_byte *data_)
|
2018-07-25 10:43:22 +01:00
|
|
|
: len (len_), data (data_)
|
|
|
|
|
{}
|
|
|
|
|
|
|
|
|
|
int len;
|
|
|
|
|
const gdb_byte *data;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Implement the push_dummy_call gdbarch method. */
|
|
|
|
|
|
|
|
|
|
static CORE_ADDR
|
|
|
|
|
csky_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
|
|
|
|
|
struct regcache *regcache, CORE_ADDR bp_addr,
|
|
|
|
|
int nargs, struct value **args, CORE_ADDR sp,
|
2018-11-16 11:21:04 +00:00
|
|
|
function_call_return_method return_method,
|
|
|
|
|
CORE_ADDR struct_addr)
|
2018-07-25 10:43:22 +01:00
|
|
|
{
|
|
|
|
|
int argnum;
|
|
|
|
|
int argreg = CSKY_ABI_A0_REGNUM;
|
|
|
|
|
int last_arg_regnum = CSKY_ABI_LAST_ARG_REGNUM;
|
|
|
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
2022-05-18 09:49:35 -06:00
|
|
|
std::vector<csky_stack_item> stack_items;
|
2018-07-25 10:43:22 +01:00
|
|
|
|
|
|
|
|
/* Set the return address. For CSKY, the return breakpoint is
|
|
|
|
|
always at BP_ADDR. */
|
|
|
|
|
regcache_cooked_write_unsigned (regcache, CSKY_LR_REGNUM, bp_addr);
|
|
|
|
|
|
|
|
|
|
/* The struct_return pointer occupies the first parameter
|
|
|
|
|
passing register. */
|
2018-11-16 11:21:04 +00:00
|
|
|
if (return_method == return_method_struct)
|
2018-07-25 10:43:22 +01:00
|
|
|
{
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: struct return in %s = %s\n",
|
|
|
|
|
gdbarch_register_name (gdbarch, argreg),
|
|
|
|
|
paddress (gdbarch, struct_addr));
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
|
|
|
|
|
argreg++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Put parameters into argument registers in REGCACHE.
|
|
|
|
|
In ABI argument registers are r0 through r3. */
|
|
|
|
|
for (argnum = 0; argnum < nargs; argnum++)
|
|
|
|
|
{
|
|
|
|
|
int len;
|
|
|
|
|
struct type *arg_type;
|
|
|
|
|
const gdb_byte *val;
|
|
|
|
|
|
2023-01-31 07:52:09 -07:00
|
|
|
arg_type = check_typedef (args[argnum]->type ());
|
2022-09-21 11:05:21 -04:00
|
|
|
len = arg_type->length ();
|
2023-01-31 14:38:30 -07:00
|
|
|
val = args[argnum]->contents ().data ();
|
2018-07-25 10:43:22 +01:00
|
|
|
|
|
|
|
|
/* Copy the argument to argument registers or the dummy stack.
|
|
|
|
|
Large arguments are split between registers and stack.
|
|
|
|
|
|
|
|
|
|
If len < 4, there is no need to worry about endianness since
|
|
|
|
|
the arguments will always be stored in the low address. */
|
|
|
|
|
if (len < 4)
|
|
|
|
|
{
|
|
|
|
|
CORE_ADDR regval
|
|
|
|
|
= extract_unsigned_integer (val, len, byte_order);
|
|
|
|
|
regcache_cooked_write_unsigned (regcache, argreg, regval);
|
|
|
|
|
argreg++;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
while (len > 0)
|
|
|
|
|
{
|
|
|
|
|
int partial_len = len < 4 ? len : 4;
|
|
|
|
|
if (argreg <= last_arg_regnum)
|
|
|
|
|
{
|
|
|
|
|
/* The argument is passed in an argument register. */
|
|
|
|
|
CORE_ADDR regval
|
|
|
|
|
= extract_unsigned_integer (val, partial_len,
|
|
|
|
|
byte_order);
|
|
|
|
|
if (byte_order == BFD_ENDIAN_BIG)
|
|
|
|
|
regval <<= (4 - partial_len) * 8;
|
|
|
|
|
|
|
|
|
|
/* Put regval into register in REGCACHE. */
|
|
|
|
|
regcache_cooked_write_unsigned (regcache, argreg,
|
|
|
|
|
regval);
|
|
|
|
|
argreg++;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* The argument should be pushed onto the dummy stack. */
|
|
|
|
|
stack_items.emplace_back (4, val);
|
|
|
|
|
}
|
|
|
|
|
len -= partial_len;
|
|
|
|
|
val += partial_len;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Transfer the dummy stack frame to the target. */
|
2022-05-18 09:49:35 -06:00
|
|
|
std::vector<csky_stack_item>::reverse_iterator iter;
|
2018-07-25 10:43:22 +01:00
|
|
|
for (iter = stack_items.rbegin (); iter != stack_items.rend (); ++iter)
|
|
|
|
|
{
|
|
|
|
|
sp -= iter->len;
|
|
|
|
|
write_memory (sp, iter->data, iter->len);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Finally, update the SP register. */
|
|
|
|
|
regcache_cooked_write_unsigned (regcache, CSKY_SP_REGNUM, sp);
|
|
|
|
|
return sp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implement the return_value gdbarch method. */
|
|
|
|
|
|
|
|
|
|
static enum return_value_convention
|
|
|
|
|
csky_return_value (struct gdbarch *gdbarch, struct value *function,
|
|
|
|
|
struct type *valtype, struct regcache *regcache,
|
|
|
|
|
gdb_byte *readbuf, const gdb_byte *writebuf)
|
|
|
|
|
{
|
|
|
|
|
CORE_ADDR regval;
|
|
|
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
2022-09-21 11:05:21 -04:00
|
|
|
int len = valtype->length ();
|
2018-07-25 10:43:22 +01:00
|
|
|
unsigned int ret_regnum = CSKY_RET_REGNUM;
|
|
|
|
|
|
|
|
|
|
/* Csky abi specifies that return values larger than 8 bytes
|
|
|
|
|
are put on the stack. */
|
|
|
|
|
if (len > 8)
|
|
|
|
|
return RETURN_VALUE_STRUCT_CONVENTION;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (readbuf != NULL)
|
|
|
|
|
{
|
|
|
|
|
ULONGEST tmp;
|
|
|
|
|
/* By using store_unsigned_integer we avoid having to do
|
|
|
|
|
anything special for small big-endian values. */
|
|
|
|
|
regcache->cooked_read (ret_regnum, &tmp);
|
|
|
|
|
store_unsigned_integer (readbuf, (len > 4 ? 4 : len),
|
|
|
|
|
byte_order, tmp);
|
|
|
|
|
if (len > 4)
|
|
|
|
|
{
|
|
|
|
|
regcache->cooked_read (ret_regnum + 1, &tmp);
|
|
|
|
|
store_unsigned_integer (readbuf + 4, 4, byte_order, tmp);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (writebuf != NULL)
|
|
|
|
|
{
|
|
|
|
|
regval = extract_unsigned_integer (writebuf, len > 4 ? 4 : len,
|
|
|
|
|
byte_order);
|
|
|
|
|
regcache_cooked_write_unsigned (regcache, ret_regnum, regval);
|
|
|
|
|
if (len > 4)
|
|
|
|
|
{
|
|
|
|
|
regval = extract_unsigned_integer ((gdb_byte *) writebuf + 4,
|
|
|
|
|
4, byte_order);
|
|
|
|
|
regcache_cooked_write_unsigned (regcache, ret_regnum + 1,
|
|
|
|
|
regval);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
return RETURN_VALUE_REGISTER_CONVENTION;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implement the frame_align gdbarch method.
|
|
|
|
|
|
|
|
|
|
Adjust the address downward (direction of stack growth) so that it
|
|
|
|
|
is correctly aligned for a new stack frame. */
|
|
|
|
|
|
|
|
|
|
static CORE_ADDR
|
|
|
|
|
csky_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
|
|
|
|
|
{
|
|
|
|
|
return align_down (addr, 4);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Unwind cache used for gdbarch fallback unwinder. */
|
|
|
|
|
|
|
|
|
|
struct csky_unwind_cache
|
|
|
|
|
{
|
|
|
|
|
/* The stack pointer at the time this frame was created; i.e. the
|
|
|
|
|
caller's stack pointer when this function was called. It is used
|
|
|
|
|
to identify this frame. */
|
|
|
|
|
CORE_ADDR prev_sp;
|
|
|
|
|
|
|
|
|
|
/* The frame base for this frame is just prev_sp - frame size.
|
|
|
|
|
FRAMESIZE is the distance from the frame pointer to the
|
|
|
|
|
initial stack pointer. */
|
|
|
|
|
int framesize;
|
|
|
|
|
|
|
|
|
|
/* The register used to hold the frame pointer for this frame. */
|
|
|
|
|
int framereg;
|
|
|
|
|
|
|
|
|
|
/* Saved register offsets. */
|
Refactor struct trad_frame_saved_regs
The following patch drops the overloading going on with the trad_frame_saved_reg
struct and defines a new struct with a KIND enum and a union of different
fields.
The new struct looks like this:
struct trad_frame_saved_reg
{
setters/getters
...
private:
trad_frame_saved_reg_kind m_kind;
union {
LONGEST value;
int realreg;
LONGEST addr;
const gdb_byte *value_bytes;
} m_reg;
};
And the enums look like this:
/* Describes the kind of encoding a stored register has. */
enum class trad_frame_saved_reg_kind
{
/* Register value is unknown. */
UNKNOWN = 0,
/* Register value is a constant. */
VALUE,
/* Register value is in another register. */
REALREG,
/* Register value is at an address. */
ADDR,
/* Register value is a sequence of bytes. */
VALUE_BYTES
};
The patch also adds setters/getters and updates all the users of the old
struct.
It is worth mentioning that due to the previous overloaded nature of the
fields, some tdep files like to store negative offsets and indexes in the ADDR
field, so I kept the ADDR as LONGEST instead of CORE_ADDR. Those cases may
be better supported by a new enum entry.
I have not addressed those cases in this patch to prevent unwanted breakage,
given I have no way to test some of the targets. But it would be nice to
clean those up eventually.
The change to frame-unwind.* is to constify the parameter being passed to the
unwinding functions, given we now accept a "const gdb_byte *" for value bytes.
Tested on aarch64-linux/Ubuntu 20.04/18.04 and by building GDB with
--enable-targets=all.
gdb/ChangeLog:
2021-01-04 Luis Machado <luis.machado@linaro.org>
Update all users of trad_frame_saved_reg to use the new member
functions.
Remote all struct keywords from declarations of trad_frame_saved_reg
types, except on forward declarations.
* aarch64-tdep.c: Update.
* alpha-mdebug-tdep.c: Update.
* alpha-tdep.c: Update.
* arc-tdep.c: Update.
* arm-tdep.c: Update.
* avr-tdep.c: Update.
* cris-tdep.c: Update.
* csky-tdep.c: Update.
* frv-tdep.c: Update.
* hppa-linux-tdep.c: Update.
* hppa-tdep.c: Update.
* hppa-tdep.h: Update.
* lm32-tdep.c: Update.
* m32r-linux-tdep.c: Update.
* m32r-tdep.c: Update.
* m68hc11-tdep.c: Update.
* mips-tdep.c: Update.
* moxie-tdep.c: Update.
* riscv-tdep.c: Update.
* rs6000-tdep.c: Update.
* s390-linux-tdep.c: Update.
* s390-tdep.c: Update.
* score-tdep.c: Update.
* sparc-netbsd-tdep.c: Update.
* sparc-sol2-tdep.c: Update.
* sparc64-fbsd-tdep.c: Update.
* sparc64-netbsd-tdep.c: Update.
* sparc64-obsd-tdep.c: Update.
* sparc64-sol2-tdep.c: Update.
* tilegx-tdep.c: Update.
* v850-tdep.c: Update.
* vax-tdep.c: Update.
* frame-unwind.c (frame_unwind_got_bytes): Make parameter const.
* frame-unwind.h (frame_unwind_got_bytes): Likewise.
* trad-frame.c: Update.
Remove TF_REG_* enum.
(trad_frame_alloc_saved_regs): Add a static assertion to check for
a trivially-constructible struct.
(trad_frame_reset_saved_regs): Adjust to use member function.
(trad_frame_value_p): Likewise.
(trad_frame_addr_p): Likewise.
(trad_frame_realreg_p): Likewise.
(trad_frame_value_bytes_p): Likewise.
(trad_frame_set_value): Likewise.
(trad_frame_set_realreg): Likewise.
(trad_frame_set_addr): Likewise.
(trad_frame_set_unknown): Likewise.
(trad_frame_set_value_bytes): Likewise.
(trad_frame_get_prev_register): Likewise.
* trad-frame.h: Update.
(trad_frame_saved_reg_kind): New enum.
(struct trad_frame_saved_reg) <addr, realreg, data>: Remove.
<m_kind, m_reg>: New member fields.
<set_value, set_realreg, set_addr, set_unknown, set_value_bytes>
<kind, value, realreg, addr, value_bytes, is_value, is_realreg>
<is_addr, is_unknown, is_value_bytes>: New member functions.
2020-12-22 17:45:21 -03:00
|
|
|
trad_frame_saved_reg *saved_regs;
|
2018-07-25 10:43:22 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Do prologue analysis, returning the PC of the first instruction
|
|
|
|
|
after the function prologue. */
|
|
|
|
|
|
|
|
|
|
static CORE_ADDR
|
|
|
|
|
csky_analyze_prologue (struct gdbarch *gdbarch,
|
|
|
|
|
CORE_ADDR start_pc,
|
|
|
|
|
CORE_ADDR limit_pc,
|
|
|
|
|
CORE_ADDR end_pc,
|
2022-07-25 14:06:35 -03:00
|
|
|
frame_info_ptr this_frame,
|
2018-07-25 10:43:22 +01:00
|
|
|
struct csky_unwind_cache *this_cache,
|
|
|
|
|
lr_type_t lr_type)
|
|
|
|
|
{
|
|
|
|
|
CORE_ADDR addr;
|
|
|
|
|
unsigned int insn, rn;
|
|
|
|
|
int framesize = 0;
|
|
|
|
|
int stacksize = 0;
|
|
|
|
|
int register_offsets[CSKY_NUM_GREGS_SAVED_GREGS];
|
|
|
|
|
int insn_len;
|
|
|
|
|
/* For adjusting fp. */
|
|
|
|
|
int is_fp_saved = 0;
|
|
|
|
|
int adjust_fp = 0;
|
|
|
|
|
|
|
|
|
|
/* REGISTER_OFFSETS will contain offsets from the top of the frame
|
|
|
|
|
(NOT the frame pointer) for the various saved registers, or -1
|
|
|
|
|
if the register is not saved. */
|
|
|
|
|
for (rn = 0; rn < CSKY_NUM_GREGS_SAVED_GREGS; rn++)
|
|
|
|
|
register_offsets[rn] = -1;
|
|
|
|
|
|
|
|
|
|
/* Analyze the prologue. Things we determine from analyzing the
|
|
|
|
|
prologue include the size of the frame and which registers are
|
|
|
|
|
saved (and where). */
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: Scanning prologue: start_pc = 0x%x,"
|
|
|
|
|
"limit_pc = 0x%x\n", (unsigned int) start_pc,
|
|
|
|
|
(unsigned int) limit_pc);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Default to 16 bit instruction. */
|
|
|
|
|
insn_len = 2;
|
|
|
|
|
stacksize = 0;
|
|
|
|
|
for (addr = start_pc; addr < limit_pc; addr += insn_len)
|
|
|
|
|
{
|
|
|
|
|
/* Get next insn. */
|
|
|
|
|
insn_len = csky_get_insn (gdbarch, addr, &insn);
|
|
|
|
|
|
|
|
|
|
/* Check if 32 bit. */
|
|
|
|
|
if (insn_len == 4)
|
|
|
|
|
{
|
|
|
|
|
/* subi32 sp,sp oimm12. */
|
|
|
|
|
if (CSKY_32_IS_SUBI0 (insn))
|
|
|
|
|
{
|
|
|
|
|
/* Got oimm12. */
|
|
|
|
|
int offset = CSKY_32_SUBI_IMM (insn);
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: got subi sp,%d; continuing\n",
|
|
|
|
|
offset);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
stacksize += offset;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
/* stm32 ry-rz,(sp). */
|
|
|
|
|
else if (CSKY_32_IS_STMx0 (insn))
|
|
|
|
|
{
|
|
|
|
|
/* Spill register(s). */
|
|
|
|
|
int start_register;
|
|
|
|
|
int reg_count;
|
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
|
|
/* BIG WARNING! The CKCore ABI does not restrict functions
|
|
|
|
|
to taking only one stack allocation. Therefore, when
|
|
|
|
|
we save a register, we record the offset of where it was
|
|
|
|
|
saved relative to the current stacksize. This will
|
|
|
|
|
then give an offset from the SP upon entry to our
|
|
|
|
|
function. Remember, stacksize is NOT constant until
|
|
|
|
|
we're done scanning the prologue. */
|
|
|
|
|
start_register = CSKY_32_STM_VAL_REGNUM (insn);
|
|
|
|
|
reg_count = CSKY_32_STM_SIZE (insn);
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: got stm r%d-r%d,(sp)\n",
|
|
|
|
|
start_register,
|
|
|
|
|
start_register + reg_count);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (rn = start_register, offset = 0;
|
|
|
|
|
rn <= start_register + reg_count;
|
|
|
|
|
rn++, offset += 4)
|
|
|
|
|
{
|
|
|
|
|
register_offsets[rn] = stacksize - offset;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: r%d saved at 0x%x"
|
|
|
|
|
" (offset %d)\n",
|
|
|
|
|
rn, register_offsets[rn],
|
|
|
|
|
offset);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (csky_debug)
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog, "csky: continuing\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
/* stw ry,(sp,disp). */
|
|
|
|
|
else if (CSKY_32_IS_STWx0 (insn))
|
|
|
|
|
{
|
|
|
|
|
/* Spill register: see note for IS_STM above. */
|
|
|
|
|
int disp;
|
|
|
|
|
|
|
|
|
|
rn = CSKY_32_ST_VAL_REGNUM (insn);
|
|
|
|
|
disp = CSKY_32_ST_OFFSET (insn);
|
|
|
|
|
register_offsets[rn] = stacksize - disp;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (rn, register_offsets, true);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_MOV_FP_SP (insn))
|
|
|
|
|
{
|
|
|
|
|
/* SP is saved to FP reg, means code afer prologue may
|
|
|
|
|
modify SP. */
|
|
|
|
|
is_fp_saved = 1;
|
|
|
|
|
adjust_fp = stacksize;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_MFCR_EPSR (insn))
|
|
|
|
|
{
|
|
|
|
|
unsigned int insn2;
|
|
|
|
|
addr += 4;
|
|
|
|
|
int mfcr_regnum = insn & 0x1f;
|
|
|
|
|
insn_len = csky_get_insn (gdbarch, addr, &insn2);
|
|
|
|
|
if (insn_len == 2)
|
|
|
|
|
{
|
|
|
|
|
int stw_regnum = (insn2 >> 5) & 0x7;
|
|
|
|
|
if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
|
|
|
|
|
{
|
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
|
|
/* CSKY_EPSR_REGNUM. */
|
|
|
|
|
rn = CSKY_NUM_GREGS;
|
|
|
|
|
offset = CSKY_16_STWx0_OFFSET (insn2);
|
|
|
|
|
register_offsets[rn] = stacksize - offset;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (rn, register_offsets, true);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* INSN_LEN == 4. */
|
|
|
|
|
int stw_regnum = (insn2 >> 21) & 0x1f;
|
|
|
|
|
if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
|
|
|
|
|
{
|
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
|
|
/* CSKY_EPSR_REGNUM. */
|
|
|
|
|
rn = CSKY_NUM_GREGS;
|
|
|
|
|
offset = CSKY_32_ST_OFFSET (insn2);
|
|
|
|
|
register_offsets[rn] = framesize - offset;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (rn, register_offsets, true);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_MFCR_FPSR (insn))
|
|
|
|
|
{
|
|
|
|
|
unsigned int insn2;
|
|
|
|
|
addr += 4;
|
|
|
|
|
int mfcr_regnum = insn & 0x1f;
|
|
|
|
|
insn_len = csky_get_insn (gdbarch, addr, &insn2);
|
|
|
|
|
if (insn_len == 2)
|
|
|
|
|
{
|
|
|
|
|
int stw_regnum = (insn2 >> 5) & 0x7;
|
|
|
|
|
if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum
|
|
|
|
|
== stw_regnum))
|
|
|
|
|
{
|
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
|
|
/* CSKY_FPSR_REGNUM. */
|
|
|
|
|
rn = CSKY_NUM_GREGS + 1;
|
|
|
|
|
offset = CSKY_16_STWx0_OFFSET (insn2);
|
|
|
|
|
register_offsets[rn] = stacksize - offset;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (rn, register_offsets, true);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* INSN_LEN == 4. */
|
|
|
|
|
int stw_regnum = (insn2 >> 21) & 0x1f;
|
|
|
|
|
if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
|
|
|
|
|
{
|
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
|
|
/* CSKY_FPSR_REGNUM. */
|
|
|
|
|
rn = CSKY_NUM_GREGS + 1;
|
|
|
|
|
offset = CSKY_32_ST_OFFSET (insn2);
|
|
|
|
|
register_offsets[rn] = framesize - offset;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (rn, register_offsets, true);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_MFCR_EPC (insn))
|
|
|
|
|
{
|
|
|
|
|
unsigned int insn2;
|
|
|
|
|
addr += 4;
|
|
|
|
|
int mfcr_regnum = insn & 0x1f;
|
|
|
|
|
insn_len = csky_get_insn (gdbarch, addr, &insn2);
|
|
|
|
|
if (insn_len == 2)
|
|
|
|
|
{
|
|
|
|
|
int stw_regnum = (insn2 >> 5) & 0x7;
|
|
|
|
|
if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
|
|
|
|
|
{
|
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
|
|
/* CSKY_EPC_REGNUM. */
|
|
|
|
|
rn = CSKY_NUM_GREGS + 2;
|
|
|
|
|
offset = CSKY_16_STWx0_OFFSET (insn2);
|
|
|
|
|
register_offsets[rn] = stacksize - offset;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (rn, register_offsets, true);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* INSN_LEN == 4. */
|
|
|
|
|
int stw_regnum = (insn2 >> 21) & 0x1f;
|
|
|
|
|
if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
|
|
|
|
|
{
|
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
|
|
/* CSKY_EPC_REGNUM. */
|
|
|
|
|
rn = CSKY_NUM_GREGS + 2;
|
|
|
|
|
offset = CSKY_32_ST_OFFSET (insn2);
|
|
|
|
|
register_offsets[rn] = framesize - offset;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (rn, register_offsets, true);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_MFCR_FPC (insn))
|
|
|
|
|
{
|
|
|
|
|
unsigned int insn2;
|
|
|
|
|
addr += 4;
|
|
|
|
|
int mfcr_regnum = insn & 0x1f;
|
|
|
|
|
insn_len = csky_get_insn (gdbarch, addr, &insn2);
|
|
|
|
|
if (insn_len == 2)
|
|
|
|
|
{
|
|
|
|
|
int stw_regnum = (insn2 >> 5) & 0x7;
|
|
|
|
|
if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
|
|
|
|
|
{
|
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
|
|
/* CSKY_FPC_REGNUM. */
|
|
|
|
|
rn = CSKY_NUM_GREGS + 3;
|
|
|
|
|
offset = CSKY_16_STWx0_OFFSET (insn2);
|
|
|
|
|
register_offsets[rn] = stacksize - offset;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (rn, register_offsets, true);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* INSN_LEN == 4. */
|
|
|
|
|
int stw_regnum = (insn2 >> 21) & 0x1f;
|
|
|
|
|
if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
|
|
|
|
|
{
|
|
|
|
|
int offset;
|
|
|
|
|
|
|
|
|
|
/* CSKY_FPC_REGNUM. */
|
|
|
|
|
rn = CSKY_NUM_GREGS + 3;
|
|
|
|
|
offset = CSKY_32_ST_OFFSET (insn2);
|
|
|
|
|
register_offsets[rn] = framesize - offset;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (rn, register_offsets, true);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_PUSH (insn))
|
|
|
|
|
{
|
|
|
|
|
/* Push for 32_bit. */
|
|
|
|
|
if (CSKY_32_IS_PUSH_R29 (insn))
|
|
|
|
|
{
|
|
|
|
|
stacksize += 4;
|
|
|
|
|
register_offsets[29] = stacksize;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (29, register_offsets, false);
|
|
|
|
|
}
|
|
|
|
|
if (CSKY_32_PUSH_LIST2 (insn))
|
|
|
|
|
{
|
|
|
|
|
int num = CSKY_32_PUSH_LIST2 (insn);
|
|
|
|
|
int tmp = 0;
|
|
|
|
|
stacksize += num * 4;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: push regs_array: r16-r%d\n",
|
|
|
|
|
16 + num - 1);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
for (rn = 16; rn <= 16 + num - 1; rn++)
|
|
|
|
|
{
|
|
|
|
|
register_offsets[rn] = stacksize - tmp;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: r%d saved at 0x%x"
|
|
|
|
|
" (offset %d)\n", rn,
|
|
|
|
|
register_offsets[rn], tmp);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
tmp += 4;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (CSKY_32_IS_PUSH_R15 (insn))
|
|
|
|
|
{
|
|
|
|
|
stacksize += 4;
|
|
|
|
|
register_offsets[15] = stacksize;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (15, register_offsets, false);
|
|
|
|
|
}
|
|
|
|
|
if (CSKY_32_PUSH_LIST1 (insn))
|
|
|
|
|
{
|
|
|
|
|
int num = CSKY_32_PUSH_LIST1 (insn);
|
|
|
|
|
int tmp = 0;
|
|
|
|
|
stacksize += num * 4;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: push regs_array: r4-r%d\n",
|
|
|
|
|
4 + num - 1);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
for (rn = 4; rn <= 4 + num - 1; rn++)
|
|
|
|
|
{
|
|
|
|
|
register_offsets[rn] = stacksize - tmp;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: r%d saved at 0x%x"
|
|
|
|
|
" (offset %d)\n", rn,
|
|
|
|
|
register_offsets[rn], tmp);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
tmp += 4;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
framesize = stacksize;
|
|
|
|
|
if (csky_debug)
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog, "csky: continuing\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_LRW4 (insn) || CSKY_32_IS_MOVI4 (insn)
|
|
|
|
|
|| CSKY_32_IS_MOVIH4 (insn) || CSKY_32_IS_BMASKI4 (insn))
|
|
|
|
|
{
|
|
|
|
|
int adjust = 0;
|
|
|
|
|
int offset = 0;
|
|
|
|
|
unsigned int insn2;
|
|
|
|
|
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: looking at large frame\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
if (CSKY_32_IS_LRW4 (insn))
|
|
|
|
|
{
|
|
|
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
|
|
|
|
int literal_addr = (addr + ((insn & 0xffff) << 2))
|
|
|
|
|
& 0xfffffffc;
|
|
|
|
|
adjust = read_memory_unsigned_integer (literal_addr, 4,
|
|
|
|
|
byte_order);
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_MOVI4 (insn))
|
|
|
|
|
adjust = (insn & 0xffff);
|
|
|
|
|
else if (CSKY_32_IS_MOVIH4 (insn))
|
|
|
|
|
adjust = (insn & 0xffff) << 16;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* CSKY_32_IS_BMASKI4 (insn). */
|
|
|
|
|
adjust = (1 << (((insn & 0x3e00000) >> 21) + 1)) - 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: base stacksize=0x%x\n", adjust);
|
2018-07-25 10:43:22 +01:00
|
|
|
|
|
|
|
|
/* May have zero or more insns which modify r4. */
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: looking for r4 adjusters...\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
offset = 4;
|
|
|
|
|
insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
|
|
|
|
|
while (CSKY_IS_R4_ADJUSTER (insn2))
|
|
|
|
|
{
|
|
|
|
|
if (CSKY_32_IS_ADDI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0xfff) + 1;
|
|
|
|
|
adjust += imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: addi r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_SUBI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0xfff) + 1;
|
|
|
|
|
adjust -= imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: subi r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_NOR4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
adjust = ~adjust;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: nor r4,r4,r4\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_ROTLI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = ((insn2 >> 21) & 0x1f);
|
|
|
|
|
int temp = adjust >> (32 - imm);
|
|
|
|
|
adjust <<= imm;
|
|
|
|
|
adjust |= temp;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: rotli r4,r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_LISI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = ((insn2 >> 21) & 0x1f);
|
|
|
|
|
adjust <<= imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: lsli r4,r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_BSETI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = ((insn2 >> 21) & 0x1f);
|
|
|
|
|
adjust |= (1 << imm);
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: bseti r4,r4 %d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_BCLRI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = ((insn2 >> 21) & 0x1f);
|
|
|
|
|
adjust &= ~(1 << imm);
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: bclri r4,r4 %d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_IXH4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
adjust *= 3;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: ixh r4,r4,r4\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_IXW4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
adjust *= 5;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: ixw r4,r4,r4\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_ADDI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0xff) + 1;
|
|
|
|
|
adjust += imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: addi r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_SUBI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0xff) + 1;
|
|
|
|
|
adjust -= imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: subi r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_NOR4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
adjust = ~adjust;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: nor r4,r4\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_BSETI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0x1f);
|
|
|
|
|
adjust |= (1 << imm);
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: bseti r4, %d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_BCLRI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0x1f);
|
|
|
|
|
adjust &= ~(1 << imm);
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: bclri r4, %d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_LSLI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0x1f);
|
|
|
|
|
adjust <<= imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: lsli r4,r4, %d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
offset += insn_len;
|
|
|
|
|
insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog, "csky: done looking for"
|
|
|
|
|
" r4 adjusters\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If the next insn adjusts the stack pointer, we keep
|
|
|
|
|
everything; if not, we scrap it and we've found the
|
|
|
|
|
end of the prologue. */
|
|
|
|
|
if (CSKY_IS_SUBU4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
addr += offset;
|
|
|
|
|
stacksize += adjust;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: found stack adjustment of"
|
|
|
|
|
" 0x%x bytes.\n", adjust);
|
|
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: skipping to new address %s\n",
|
|
|
|
|
core_addr_to_string_nz (addr));
|
|
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: continuing\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* None of these instructions are prologue, so don't touch
|
|
|
|
|
anything. */
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: no subu sp,sp,r4; NOT altering"
|
|
|
|
|
" stacksize.\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* insn_len != 4. */
|
|
|
|
|
|
|
|
|
|
/* subi.sp sp,disp. */
|
|
|
|
|
if (CSKY_16_IS_SUBI0 (insn))
|
|
|
|
|
{
|
|
|
|
|
int offset = CSKY_16_SUBI_IMM (insn);
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: got subi r0,%d; continuing\n",
|
|
|
|
|
offset);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
stacksize += offset;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
/* stw.16 rz,(sp,disp). */
|
|
|
|
|
else if (CSKY_16_IS_STWx0 (insn))
|
|
|
|
|
{
|
|
|
|
|
/* Spill register: see note for IS_STM above. */
|
|
|
|
|
int disp;
|
|
|
|
|
|
|
|
|
|
rn = CSKY_16_ST_VAL_REGNUM (insn);
|
|
|
|
|
disp = CSKY_16_ST_OFFSET (insn);
|
|
|
|
|
register_offsets[rn] = stacksize - disp;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (rn, register_offsets, true);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_MOV_FP_SP (insn))
|
|
|
|
|
{
|
|
|
|
|
/* SP is saved to FP reg, means prologue may modify SP. */
|
|
|
|
|
is_fp_saved = 1;
|
|
|
|
|
adjust_fp = stacksize;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_PUSH (insn))
|
|
|
|
|
{
|
|
|
|
|
/* Push for 16_bit. */
|
|
|
|
|
int offset = 0;
|
|
|
|
|
if (CSKY_16_IS_PUSH_R15 (insn))
|
|
|
|
|
{
|
|
|
|
|
stacksize += 4;
|
|
|
|
|
register_offsets[15] = stacksize;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
print_savedreg_msg (15, register_offsets, false);
|
|
|
|
|
offset += 4;
|
|
|
|
|
}
|
|
|
|
|
if (CSKY_16_PUSH_LIST1 (insn))
|
|
|
|
|
{
|
|
|
|
|
int num = CSKY_16_PUSH_LIST1 (insn);
|
|
|
|
|
int tmp = 0;
|
|
|
|
|
stacksize += num * 4;
|
|
|
|
|
offset += num * 4;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: push regs_array: r4-r%d\n",
|
|
|
|
|
4 + num - 1);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
for (rn = 4; rn <= 4 + num - 1; rn++)
|
|
|
|
|
{
|
|
|
|
|
register_offsets[rn] = stacksize - tmp;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: r%d saved at 0x%x"
|
|
|
|
|
" (offset %d)\n", rn,
|
|
|
|
|
register_offsets[rn], offset);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
tmp += 4;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
framesize = stacksize;
|
|
|
|
|
if (csky_debug)
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog, "csky: continuing\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_LRW4 (insn) || CSKY_16_IS_MOVI4 (insn))
|
|
|
|
|
{
|
|
|
|
|
int adjust = 0;
|
|
|
|
|
unsigned int insn2;
|
|
|
|
|
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: looking at large frame\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
if (CSKY_16_IS_LRW4 (insn))
|
|
|
|
|
{
|
|
|
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
|
|
|
|
int offset = ((insn & 0x300) >> 3) | (insn & 0x1f);
|
|
|
|
|
int literal_addr = (addr + ( offset << 2)) & 0xfffffffc;
|
|
|
|
|
adjust = read_memory_unsigned_integer (literal_addr, 4,
|
|
|
|
|
byte_order);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* CSKY_16_IS_MOVI4 (insn). */
|
|
|
|
|
adjust = (insn & 0xff);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: base stacksize=0x%x\n", adjust);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* May have zero or more instructions which modify r4. */
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: looking for r4 adjusters...\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
2018-04-21 16:16:27 -06:00
|
|
|
int offset = 2;
|
2018-07-25 10:43:22 +01:00
|
|
|
insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
|
|
|
|
|
while (CSKY_IS_R4_ADJUSTER (insn2))
|
|
|
|
|
{
|
|
|
|
|
if (CSKY_32_IS_ADDI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0xfff) + 1;
|
|
|
|
|
adjust += imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: addi r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_SUBI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0xfff) + 1;
|
|
|
|
|
adjust -= imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: subi r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_NOR4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
adjust = ~adjust;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: nor r4,r4,r4\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_ROTLI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = ((insn2 >> 21) & 0x1f);
|
|
|
|
|
int temp = adjust >> (32 - imm);
|
|
|
|
|
adjust <<= imm;
|
|
|
|
|
adjust |= temp;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: rotli r4,r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_LISI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = ((insn2 >> 21) & 0x1f);
|
|
|
|
|
adjust <<= imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: lsli r4,r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_BSETI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = ((insn2 >> 21) & 0x1f);
|
|
|
|
|
adjust |= (1 << imm);
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: bseti r4,r4 %d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_BCLRI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = ((insn2 >> 21) & 0x1f);
|
|
|
|
|
adjust &= ~(1 << imm);
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: bclri r4,r4 %d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_IXH4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
adjust *= 3;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: ixh r4,r4,r4\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_IXW4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
adjust *= 5;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: ixw r4,r4,r4\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_ADDI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0xff) + 1;
|
|
|
|
|
adjust += imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: addi r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_SUBI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0xff) + 1;
|
|
|
|
|
adjust -= imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: subi r4,%d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_NOR4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
adjust = ~adjust;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: nor r4,r4\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_BSETI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0x1f);
|
|
|
|
|
adjust |= (1 << imm);
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: bseti r4, %d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_BCLRI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0x1f);
|
|
|
|
|
adjust &= ~(1 << imm);
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: bclri r4, %d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_16_IS_LSLI4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
int imm = (insn2 & 0x1f);
|
|
|
|
|
adjust <<= imm;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog,
|
|
|
|
|
"csky: lsli r4,r4, %d\n", imm);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
offset += insn_len;
|
|
|
|
|
insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog, "csky: "
|
|
|
|
|
"done looking for r4 adjusters\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If the next instruction adjusts the stack pointer, we keep
|
|
|
|
|
everything; if not, we scrap it and we've found the end
|
|
|
|
|
of the prologue. */
|
|
|
|
|
if (CSKY_IS_SUBU4 (insn2))
|
|
|
|
|
{
|
|
|
|
|
addr += offset;
|
|
|
|
|
stacksize += adjust;
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog, "csky: "
|
|
|
|
|
"found stack adjustment of 0x%x"
|
|
|
|
|
" bytes.\n", adjust);
|
|
|
|
|
gdb_printf (gdb_stdlog, "csky: "
|
|
|
|
|
"skipping to new address %s\n",
|
|
|
|
|
core_addr_to_string_nz (addr));
|
|
|
|
|
gdb_printf (gdb_stdlog, "csky: continuing\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* None of these instructions are prologue, so don't touch
|
|
|
|
|
anything. */
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog, "csky: no subu sp,r4; "
|
|
|
|
|
"NOT altering stacksize.\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This is not a prologue instruction, so stop here. */
|
|
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog, "csky: insn is not a prologue"
|
|
|
|
|
" insn -- ending scan\n");
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (this_cache)
|
|
|
|
|
{
|
|
|
|
|
CORE_ADDR unwound_fp;
|
|
|
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
|
|
|
|
this_cache->framesize = framesize;
|
|
|
|
|
|
|
|
|
|
if (is_fp_saved)
|
|
|
|
|
{
|
|
|
|
|
this_cache->framereg = CSKY_FP_REGNUM;
|
|
|
|
|
unwound_fp = get_frame_register_unsigned (this_frame,
|
|
|
|
|
this_cache->framereg);
|
|
|
|
|
this_cache->prev_sp = unwound_fp + adjust_fp;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
this_cache->framereg = CSKY_SP_REGNUM;
|
|
|
|
|
unwound_fp = get_frame_register_unsigned (this_frame,
|
|
|
|
|
this_cache->framereg);
|
|
|
|
|
this_cache->prev_sp = unwound_fp + stacksize;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Note where saved registers are stored. The offsets in
|
|
|
|
|
REGISTER_OFFSETS are computed relative to the top of the frame. */
|
|
|
|
|
for (rn = 0; rn < CSKY_NUM_GREGS; rn++)
|
|
|
|
|
{
|
|
|
|
|
if (register_offsets[rn] >= 0)
|
|
|
|
|
{
|
Refactor struct trad_frame_saved_regs
The following patch drops the overloading going on with the trad_frame_saved_reg
struct and defines a new struct with a KIND enum and a union of different
fields.
The new struct looks like this:
struct trad_frame_saved_reg
{
setters/getters
...
private:
trad_frame_saved_reg_kind m_kind;
union {
LONGEST value;
int realreg;
LONGEST addr;
const gdb_byte *value_bytes;
} m_reg;
};
And the enums look like this:
/* Describes the kind of encoding a stored register has. */
enum class trad_frame_saved_reg_kind
{
/* Register value is unknown. */
UNKNOWN = 0,
/* Register value is a constant. */
VALUE,
/* Register value is in another register. */
REALREG,
/* Register value is at an address. */
ADDR,
/* Register value is a sequence of bytes. */
VALUE_BYTES
};
The patch also adds setters/getters and updates all the users of the old
struct.
It is worth mentioning that due to the previous overloaded nature of the
fields, some tdep files like to store negative offsets and indexes in the ADDR
field, so I kept the ADDR as LONGEST instead of CORE_ADDR. Those cases may
be better supported by a new enum entry.
I have not addressed those cases in this patch to prevent unwanted breakage,
given I have no way to test some of the targets. But it would be nice to
clean those up eventually.
The change to frame-unwind.* is to constify the parameter being passed to the
unwinding functions, given we now accept a "const gdb_byte *" for value bytes.
Tested on aarch64-linux/Ubuntu 20.04/18.04 and by building GDB with
--enable-targets=all.
gdb/ChangeLog:
2021-01-04 Luis Machado <luis.machado@linaro.org>
Update all users of trad_frame_saved_reg to use the new member
functions.
Remote all struct keywords from declarations of trad_frame_saved_reg
types, except on forward declarations.
* aarch64-tdep.c: Update.
* alpha-mdebug-tdep.c: Update.
* alpha-tdep.c: Update.
* arc-tdep.c: Update.
* arm-tdep.c: Update.
* avr-tdep.c: Update.
* cris-tdep.c: Update.
* csky-tdep.c: Update.
* frv-tdep.c: Update.
* hppa-linux-tdep.c: Update.
* hppa-tdep.c: Update.
* hppa-tdep.h: Update.
* lm32-tdep.c: Update.
* m32r-linux-tdep.c: Update.
* m32r-tdep.c: Update.
* m68hc11-tdep.c: Update.
* mips-tdep.c: Update.
* moxie-tdep.c: Update.
* riscv-tdep.c: Update.
* rs6000-tdep.c: Update.
* s390-linux-tdep.c: Update.
* s390-tdep.c: Update.
* score-tdep.c: Update.
* sparc-netbsd-tdep.c: Update.
* sparc-sol2-tdep.c: Update.
* sparc64-fbsd-tdep.c: Update.
* sparc64-netbsd-tdep.c: Update.
* sparc64-obsd-tdep.c: Update.
* sparc64-sol2-tdep.c: Update.
* tilegx-tdep.c: Update.
* v850-tdep.c: Update.
* vax-tdep.c: Update.
* frame-unwind.c (frame_unwind_got_bytes): Make parameter const.
* frame-unwind.h (frame_unwind_got_bytes): Likewise.
* trad-frame.c: Update.
Remove TF_REG_* enum.
(trad_frame_alloc_saved_regs): Add a static assertion to check for
a trivially-constructible struct.
(trad_frame_reset_saved_regs): Adjust to use member function.
(trad_frame_value_p): Likewise.
(trad_frame_addr_p): Likewise.
(trad_frame_realreg_p): Likewise.
(trad_frame_value_bytes_p): Likewise.
(trad_frame_set_value): Likewise.
(trad_frame_set_realreg): Likewise.
(trad_frame_set_addr): Likewise.
(trad_frame_set_unknown): Likewise.
(trad_frame_set_value_bytes): Likewise.
(trad_frame_get_prev_register): Likewise.
* trad-frame.h: Update.
(trad_frame_saved_reg_kind): New enum.
(struct trad_frame_saved_reg) <addr, realreg, data>: Remove.
<m_kind, m_reg>: New member fields.
<set_value, set_realreg, set_addr, set_unknown, set_value_bytes>
<kind, value, realreg, addr, value_bytes, is_value, is_realreg>
<is_addr, is_unknown, is_value_bytes>: New member functions.
2020-12-22 17:45:21 -03:00
|
|
|
this_cache->saved_regs[rn].set_addr (this_cache->prev_sp
|
|
|
|
|
- register_offsets[rn]);
|
2018-07-25 10:43:22 +01:00
|
|
|
if (csky_debug)
|
|
|
|
|
{
|
|
|
|
|
CORE_ADDR rn_value = read_memory_unsigned_integer (
|
Refactor struct trad_frame_saved_regs
The following patch drops the overloading going on with the trad_frame_saved_reg
struct and defines a new struct with a KIND enum and a union of different
fields.
The new struct looks like this:
struct trad_frame_saved_reg
{
setters/getters
...
private:
trad_frame_saved_reg_kind m_kind;
union {
LONGEST value;
int realreg;
LONGEST addr;
const gdb_byte *value_bytes;
} m_reg;
};
And the enums look like this:
/* Describes the kind of encoding a stored register has. */
enum class trad_frame_saved_reg_kind
{
/* Register value is unknown. */
UNKNOWN = 0,
/* Register value is a constant. */
VALUE,
/* Register value is in another register. */
REALREG,
/* Register value is at an address. */
ADDR,
/* Register value is a sequence of bytes. */
VALUE_BYTES
};
The patch also adds setters/getters and updates all the users of the old
struct.
It is worth mentioning that due to the previous overloaded nature of the
fields, some tdep files like to store negative offsets and indexes in the ADDR
field, so I kept the ADDR as LONGEST instead of CORE_ADDR. Those cases may
be better supported by a new enum entry.
I have not addressed those cases in this patch to prevent unwanted breakage,
given I have no way to test some of the targets. But it would be nice to
clean those up eventually.
The change to frame-unwind.* is to constify the parameter being passed to the
unwinding functions, given we now accept a "const gdb_byte *" for value bytes.
Tested on aarch64-linux/Ubuntu 20.04/18.04 and by building GDB with
--enable-targets=all.
gdb/ChangeLog:
2021-01-04 Luis Machado <luis.machado@linaro.org>
Update all users of trad_frame_saved_reg to use the new member
functions.
Remote all struct keywords from declarations of trad_frame_saved_reg
types, except on forward declarations.
* aarch64-tdep.c: Update.
* alpha-mdebug-tdep.c: Update.
* alpha-tdep.c: Update.
* arc-tdep.c: Update.
* arm-tdep.c: Update.
* avr-tdep.c: Update.
* cris-tdep.c: Update.
* csky-tdep.c: Update.
* frv-tdep.c: Update.
* hppa-linux-tdep.c: Update.
* hppa-tdep.c: Update.
* hppa-tdep.h: Update.
* lm32-tdep.c: Update.
* m32r-linux-tdep.c: Update.
* m32r-tdep.c: Update.
* m68hc11-tdep.c: Update.
* mips-tdep.c: Update.
* moxie-tdep.c: Update.
* riscv-tdep.c: Update.
* rs6000-tdep.c: Update.
* s390-linux-tdep.c: Update.
* s390-tdep.c: Update.
* score-tdep.c: Update.
* sparc-netbsd-tdep.c: Update.
* sparc-sol2-tdep.c: Update.
* sparc64-fbsd-tdep.c: Update.
* sparc64-netbsd-tdep.c: Update.
* sparc64-obsd-tdep.c: Update.
* sparc64-sol2-tdep.c: Update.
* tilegx-tdep.c: Update.
* v850-tdep.c: Update.
* vax-tdep.c: Update.
* frame-unwind.c (frame_unwind_got_bytes): Make parameter const.
* frame-unwind.h (frame_unwind_got_bytes): Likewise.
* trad-frame.c: Update.
Remove TF_REG_* enum.
(trad_frame_alloc_saved_regs): Add a static assertion to check for
a trivially-constructible struct.
(trad_frame_reset_saved_regs): Adjust to use member function.
(trad_frame_value_p): Likewise.
(trad_frame_addr_p): Likewise.
(trad_frame_realreg_p): Likewise.
(trad_frame_value_bytes_p): Likewise.
(trad_frame_set_value): Likewise.
(trad_frame_set_realreg): Likewise.
(trad_frame_set_addr): Likewise.
(trad_frame_set_unknown): Likewise.
(trad_frame_set_value_bytes): Likewise.
(trad_frame_get_prev_register): Likewise.
* trad-frame.h: Update.
(trad_frame_saved_reg_kind): New enum.
(struct trad_frame_saved_reg) <addr, realreg, data>: Remove.
<m_kind, m_reg>: New member fields.
<set_value, set_realreg, set_addr, set_unknown, set_value_bytes>
<kind, value, realreg, addr, value_bytes, is_value, is_realreg>
<is_addr, is_unknown, is_value_bytes>: New member functions.
2020-12-22 17:45:21 -03:00
|
|
|
this_cache->saved_regs[rn].addr (), 4, byte_order);
|
2022-01-02 11:46:15 -07:00
|
|
|
gdb_printf (gdb_stdlog, "Saved register %s "
|
|
|
|
|
"stored at 0x%08lx, value=0x%08lx\n",
|
|
|
|
|
csky_register_names[rn],
|
|
|
|
|
(unsigned long)
|
|
|
|
|
this_cache->saved_regs[rn].addr (),
|
|
|
|
|
(unsigned long) rn_value);
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (lr_type == LR_TYPE_EPC)
|
|
|
|
|
{
|
|
|
|
|
/* rte || epc . */
|
|
|
|
|
this_cache->saved_regs[CSKY_PC_REGNUM]
|
|
|
|
|
= this_cache->saved_regs[CSKY_EPC_REGNUM];
|
|
|
|
|
}
|
|
|
|
|
else if (lr_type == LR_TYPE_FPC)
|
|
|
|
|
{
|
|
|
|
|
/* rfi || fpc . */
|
|
|
|
|
this_cache->saved_regs[CSKY_PC_REGNUM]
|
|
|
|
|
= this_cache->saved_regs[CSKY_FPC_REGNUM];
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
this_cache->saved_regs[CSKY_PC_REGNUM]
|
|
|
|
|
= this_cache->saved_regs[CSKY_LR_REGNUM];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return addr;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Detect whether PC is at a point where the stack frame has been
|
|
|
|
|
destroyed. */
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
csky_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
|
|
|
|
|
{
|
|
|
|
|
unsigned int insn;
|
|
|
|
|
CORE_ADDR addr;
|
|
|
|
|
CORE_ADDR func_start, func_end;
|
|
|
|
|
|
|
|
|
|
if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
bool fp_saved = false;
|
|
|
|
|
int insn_len;
|
|
|
|
|
for (addr = func_start; addr < func_end; addr += insn_len)
|
|
|
|
|
{
|
|
|
|
|
/* Get next insn. */
|
|
|
|
|
insn_len = csky_get_insn (gdbarch, addr, &insn);
|
|
|
|
|
|
|
|
|
|
if (insn_len == 2)
|
|
|
|
|
{
|
|
|
|
|
/* Is sp is saved to fp. */
|
|
|
|
|
if (CSKY_16_IS_MOV_FP_SP (insn))
|
|
|
|
|
fp_saved = true;
|
|
|
|
|
/* If sp was saved to fp and now being restored from
|
|
|
|
|
fp then it indicates the start of epilog. */
|
|
|
|
|
else if (fp_saved && CSKY_16_IS_MOV_SP_FP (insn))
|
|
|
|
|
return pc >= addr;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implement the skip_prologue gdbarch hook. */
|
|
|
|
|
|
|
|
|
|
static CORE_ADDR
|
|
|
|
|
csky_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
|
|
|
|
|
{
|
|
|
|
|
CORE_ADDR func_addr, func_end;
|
|
|
|
|
const int default_search_limit = 128;
|
|
|
|
|
|
|
|
|
|
/* See if we can find the end of the prologue using the symbol table. */
|
|
|
|
|
if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
|
|
|
|
|
{
|
|
|
|
|
CORE_ADDR post_prologue_pc
|
|
|
|
|
= skip_prologue_using_sal (gdbarch, func_addr);
|
|
|
|
|
|
|
|
|
|
if (post_prologue_pc != 0)
|
|
|
|
|
return std::max (pc, post_prologue_pc);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
func_end = pc + default_search_limit;
|
|
|
|
|
|
|
|
|
|
/* Find the end of prologue. Default lr_type. */
|
|
|
|
|
return csky_analyze_prologue (gdbarch, pc, func_end, func_end,
|
|
|
|
|
NULL, NULL, LR_TYPE_R15);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implement the breakpoint_kind_from_pc gdbarch method. */
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
csky_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
|
|
|
|
|
{
|
|
|
|
|
if (csky_pc_is_csky16 (gdbarch, *pcptr))
|
|
|
|
|
return CSKY_INSN_SIZE16;
|
|
|
|
|
else
|
|
|
|
|
return CSKY_INSN_SIZE32;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implement the sw_breakpoint_from_kind gdbarch method. */
|
|
|
|
|
|
|
|
|
|
static const gdb_byte *
|
|
|
|
|
csky_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
|
|
|
|
|
{
|
|
|
|
|
*size = kind;
|
|
|
|
|
if (kind == CSKY_INSN_SIZE16)
|
|
|
|
|
{
|
|
|
|
|
static gdb_byte csky_16_breakpoint[] = { 0, 0 };
|
|
|
|
|
return csky_16_breakpoint;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
static gdb_byte csky_32_breakpoint[] = { 0, 0, 0, 0 };
|
|
|
|
|
return csky_32_breakpoint;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Determine link register type. */
|
|
|
|
|
|
|
|
|
|
static lr_type_t
|
|
|
|
|
csky_analyze_lr_type (struct gdbarch *gdbarch,
|
|
|
|
|
CORE_ADDR start_pc, CORE_ADDR end_pc)
|
|
|
|
|
{
|
|
|
|
|
CORE_ADDR addr;
|
|
|
|
|
unsigned int insn, insn_len;
|
|
|
|
|
insn_len = 2;
|
|
|
|
|
|
|
|
|
|
for (addr = start_pc; addr < end_pc; addr += insn_len)
|
|
|
|
|
{
|
|
|
|
|
insn_len = csky_get_insn (gdbarch, addr, &insn);
|
|
|
|
|
if (insn_len == 4)
|
|
|
|
|
{
|
|
|
|
|
if (CSKY_32_IS_MFCR_EPSR (insn) || CSKY_32_IS_MFCR_EPC (insn)
|
|
|
|
|
|| CSKY_32_IS_RTE (insn))
|
|
|
|
|
return LR_TYPE_EPC;
|
|
|
|
|
}
|
|
|
|
|
else if (CSKY_32_IS_MFCR_FPSR (insn) || CSKY_32_IS_MFCR_FPC (insn)
|
|
|
|
|
|| CSKY_32_IS_RFI (insn))
|
|
|
|
|
return LR_TYPE_FPC;
|
|
|
|
|
else if (CSKY_32_IS_JMP (insn) || CSKY_32_IS_BR (insn)
|
|
|
|
|
|| CSKY_32_IS_JMPIX (insn) || CSKY_32_IS_JMPI (insn))
|
|
|
|
|
return LR_TYPE_R15;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* 16 bit instruction. */
|
|
|
|
|
if (CSKY_16_IS_JMP (insn) || CSKY_16_IS_BR (insn)
|
|
|
|
|
|| CSKY_16_IS_JMPIX (insn))
|
|
|
|
|
return LR_TYPE_R15;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return LR_TYPE_R15;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Heuristic unwinder. */
|
|
|
|
|
|
|
|
|
|
static struct csky_unwind_cache *
|
2022-07-25 14:06:35 -03:00
|
|
|
csky_frame_unwind_cache (frame_info_ptr this_frame)
|
2018-07-25 10:43:22 +01:00
|
|
|
{
|
|
|
|
|
CORE_ADDR prologue_start, prologue_end, func_end, prev_pc, block_addr;
|
|
|
|
|
struct csky_unwind_cache *cache;
|
|
|
|
|
const struct block *bl;
|
|
|
|
|
unsigned long func_size = 0;
|
|
|
|
|
struct gdbarch *gdbarch = get_frame_arch (this_frame);
|
|
|
|
|
unsigned int sp_regnum = CSKY_SP_REGNUM;
|
|
|
|
|
|
|
|
|
|
/* Default lr type is r15. */
|
|
|
|
|
lr_type_t lr_type = LR_TYPE_R15;
|
|
|
|
|
|
|
|
|
|
cache = FRAME_OBSTACK_ZALLOC (struct csky_unwind_cache);
|
|
|
|
|
cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
|
|
|
|
|
|
|
|
|
|
/* Assume there is no frame until proven otherwise. */
|
|
|
|
|
cache->framereg = sp_regnum;
|
|
|
|
|
|
|
|
|
|
cache->framesize = 0;
|
|
|
|
|
|
|
|
|
|
prev_pc = get_frame_pc (this_frame);
|
|
|
|
|
block_addr = get_frame_address_in_block (this_frame);
|
|
|
|
|
if (find_pc_partial_function (block_addr, NULL, &prologue_start,
|
|
|
|
|
&func_end) == 0)
|
|
|
|
|
/* We couldn't find a function containing block_addr, so bail out
|
|
|
|
|
and hope for the best. */
|
|
|
|
|
return cache;
|
|
|
|
|
|
|
|
|
|
/* Get the (function) symbol matching prologue_start. */
|
|
|
|
|
bl = block_for_pc (prologue_start);
|
|
|
|
|
if (bl != NULL)
|
2022-01-28 10:59:38 -05:00
|
|
|
func_size = bl->end () - bl->start ();
|
2018-07-25 10:43:22 +01:00
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
struct bound_minimal_symbol msymbol
|
|
|
|
|
= lookup_minimal_symbol_by_pc (prologue_start);
|
|
|
|
|
if (msymbol.minsym != NULL)
|
2022-01-28 10:41:49 -05:00
|
|
|
func_size = msymbol.minsym->size ();
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If FUNC_SIZE is 0 we may have a special-case use of lr
|
|
|
|
|
e.g. exception or interrupt. */
|
|
|
|
|
if (func_size == 0)
|
|
|
|
|
lr_type = csky_analyze_lr_type (gdbarch, prologue_start, func_end);
|
|
|
|
|
|
|
|
|
|
prologue_end = std::min (func_end, prev_pc);
|
|
|
|
|
|
|
|
|
|
/* Analyze the function prologue. */
|
|
|
|
|
csky_analyze_prologue (gdbarch, prologue_start, prologue_end,
|
|
|
|
|
func_end, this_frame, cache, lr_type);
|
|
|
|
|
|
|
|
|
|
/* gdbarch_sp_regnum contains the value and not the address. */
|
trad-frame cleanups
With the new member functions for struct trad_frame_saved_reg, there is no
need to invoke some of the set/get functions anymore. This patch removes
those and adjusts all callers.
Even though the most natural initial state of a saved register value is
UNKNOWN, there are target backends relying on the previous initial state
of REALREG set to a register's own number. I noticed this in at least a
couple targets: aarch64 and riscv.
Because of that, I decided to keep the reset function that sets the set of
register values to REALREG. I can't exercise all the targets to make sure
the initial state change won't break things, hence why it is risky to change
the default.
Validated with --enable-targets=all on aarch64-linux Ubuntu 18.04/20.04.
gdb/ChangeLog
2021-01-19 Luis Machado <luis.machado@linaro.org>
* trad-frame.h (trad_frame_saved_reg) <set_value_bytes>: Allocate
memory and save data.
(trad_frame_set_value, trad_frame_set_realreg, trad_frame_set_addr)
(trad_frame_set_unknown, trad_frame_set_value_bytes)
(trad_frame_value_p, trad_frame_addr_p, trad_frame_realreg_p)
(trad_frame_value_bytes_p): Remove.
(trad_frame_reset_saved_regs): Adjust documentation.
* trad-frame.c (trad_frame_alloc_saved_regs): Initialize via a
constructor and reset the state of the registers.
(trad_frame_value_p, trad_frame_addr_p, trad_frame_realreg_p)
(trad_frame_value_bytes_p, trad_frame_set_value)
(trad_frame_set_realreg, trad_frame_set_addr)
(trad_frame_set_unknown, trad_frame_set_value_bytes): Remove.
(trad_frame_set_reg_realreg): Update to call member function.
(trad_frame_set_reg_addr, trad_frame_set_reg_value_bytes): Likewise.
(trad_frame_get_prev_register): Likewise.
* aarch64-tdep.c (aarch64_analyze_prologue)
(aarch64_analyze_prologue_test, aarch64_make_prologue_cache_1)
(aarch64_prologue_prev_register): Update to use member functions.
* alpha-mdebug-tdep.c (alpha_mdebug_frame_unwind_cache): Likewise.
* alpha-tdep.c (alpha_heuristic_frame_unwind_cache): Likewise.
* arc-tdep.c (arc_print_frame_cache, arc_make_frame_cache): Likewise.
* arm-tdep.c (arm_make_prologue_cache, arm_exidx_fill_cache)
(arm_make_epilogue_frame_cache): Likewise.
* avr-tdep.c (avr_frame_unwind_cache)
(avr_frame_prev_register): Likewise.
* cris-tdep.c (cris_scan_prologue): Likewise.
* csky-tdep.c (csky_frame_unwind_cache): Likewise.
* frv-tdep.c (frv_analyze_prologue): Likewise.
* hppa-tdep.c (hppa_frame_cache, hppa_fallback_frame_cache): Likewise.
* lm32-tdep.c (lm32_frame_cache): Likewise.
* m32r-tdep.c (m32r_frame_unwind_cache): Likewise.
* m68hc11-tdep.c (m68hc11_frame_unwind_cache): Likewise.
* mips-tdep.c (set_reg_offset, mips_insn16_frame_cache)
(mips_micro_frame_cache, mips_insn32_frame_cache): Likewise.
(reset_saved_regs): Adjust to set realreg.
* riscv-tdep.c (riscv_scan_prologue, riscv_frame_cache): Adjust to
call member functions.
* rs6000-tdep.c (rs6000_frame_cache, rs6000_epilogue_frame_cache)
* s390-tdep.c (s390_prologue_frame_unwind_cache)
(s390_backchain_frame_unwind_cache): Likewise.
* score-tdep.c (score7_analyze_prologue)
(score3_analyze_prologue, score_make_prologue_cache): Likewise.
* sparc-netbsd-tdep.c (sparc32nbsd_sigcontext_saved_regs): Likewise.
* sparc-sol2-tdep.c (sparc32_sol2_sigtramp_frame_cache): Likewise.
* sparc64-netbsd-tdep.c (sparc64nbsd_sigcontext_saved_regs): Likewise.
* sparc64-sol2-tdep.c (sparc64_sol2_sigtramp_frame_cache): Likewise.
* tilegx-tdep.c (tilegx_analyze_prologue)
(tilegx_frame_cache): Likewise.
* v850-tdep.c (v850_frame_cache): Likewise.
* vax-tdep.c (vax_frame_cache): Likewise.
2021-01-14 15:43:28 -03:00
|
|
|
cache->saved_regs[sp_regnum].set_value (cache->prev_sp);
|
2018-07-25 10:43:22 +01:00
|
|
|
return cache;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implement the this_id function for the normal unwinder. */
|
|
|
|
|
|
|
|
|
|
static void
|
2022-07-25 14:06:35 -03:00
|
|
|
csky_frame_this_id (frame_info_ptr this_frame,
|
2018-07-25 10:43:22 +01:00
|
|
|
void **this_prologue_cache, struct frame_id *this_id)
|
|
|
|
|
{
|
|
|
|
|
struct csky_unwind_cache *cache;
|
|
|
|
|
struct frame_id id;
|
|
|
|
|
|
|
|
|
|
if (*this_prologue_cache == NULL)
|
|
|
|
|
*this_prologue_cache = csky_frame_unwind_cache (this_frame);
|
|
|
|
|
cache = (struct csky_unwind_cache *) *this_prologue_cache;
|
|
|
|
|
|
|
|
|
|
/* This marks the outermost frame. */
|
|
|
|
|
if (cache->prev_sp == 0)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
id = frame_id_build (cache->prev_sp, get_frame_func (this_frame));
|
|
|
|
|
*this_id = id;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implement the prev_register function for the normal unwinder. */
|
|
|
|
|
|
|
|
|
|
static struct value *
|
2022-07-25 14:06:35 -03:00
|
|
|
csky_frame_prev_register (frame_info_ptr this_frame,
|
2018-07-25 10:43:22 +01:00
|
|
|
void **this_prologue_cache, int regnum)
|
|
|
|
|
{
|
|
|
|
|
struct csky_unwind_cache *cache;
|
|
|
|
|
|
|
|
|
|
if (*this_prologue_cache == NULL)
|
|
|
|
|
*this_prologue_cache = csky_frame_unwind_cache (this_frame);
|
|
|
|
|
cache = (struct csky_unwind_cache *) *this_prologue_cache;
|
|
|
|
|
|
|
|
|
|
return trad_frame_get_prev_register (this_frame, cache->saved_regs,
|
|
|
|
|
regnum);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Data structures for the normal prologue-analysis-based
|
|
|
|
|
unwinder. */
|
|
|
|
|
|
|
|
|
|
static const struct frame_unwind csky_unwind_cache = {
|
2021-06-29 12:05:03 -04:00
|
|
|
"cski prologue",
|
2018-07-25 10:43:22 +01:00
|
|
|
NORMAL_FRAME,
|
|
|
|
|
default_frame_unwind_stop_reason,
|
|
|
|
|
csky_frame_this_id,
|
|
|
|
|
csky_frame_prev_register,
|
|
|
|
|
NULL,
|
|
|
|
|
default_frame_sniffer,
|
|
|
|
|
NULL,
|
|
|
|
|
NULL
|
|
|
|
|
};
|
|
|
|
|
|
2022-09-13 14:19:26 +08:00
|
|
|
static CORE_ADDR
|
2022-07-25 14:06:35 -03:00
|
|
|
csky_check_long_branch (frame_info_ptr frame, CORE_ADDR pc)
|
2022-09-13 14:19:26 +08:00
|
|
|
{
|
|
|
|
|
gdb_byte buf[8];
|
|
|
|
|
struct gdbarch *gdbarch = get_frame_arch (frame);
|
|
|
|
|
enum bfd_endian byte_order_for_code
|
|
|
|
|
= gdbarch_byte_order_for_code (gdbarch);
|
|
|
|
|
|
|
|
|
|
if (target_read_memory (pc, buf, 8) == 0)
|
|
|
|
|
{
|
|
|
|
|
unsigned int data0
|
|
|
|
|
= extract_unsigned_integer (buf, 4, byte_order_for_code);
|
|
|
|
|
unsigned int data1
|
|
|
|
|
= extract_unsigned_integer (buf + 4, 4, byte_order_for_code);
|
|
|
|
|
|
|
|
|
|
/* Case: jmpi [pc+4] : 0xeac00001
|
|
|
|
|
.long addr */
|
|
|
|
|
if (data0 == CSKY_JMPI_PC_4)
|
|
|
|
|
return data1;
|
|
|
|
|
|
|
|
|
|
/* Case: lrw t1, [pc+8] : 0xea8d0002
|
|
|
|
|
jmp t1 : 0x7834
|
|
|
|
|
nop : 0x6c03
|
|
|
|
|
.long addr */
|
|
|
|
|
if ((data0 == CSKY_LRW_T1_PC_8) && (data1 == CSKY_JMP_T1_VS_NOP))
|
|
|
|
|
{
|
|
|
|
|
if (target_read_memory (pc + 8, buf, 4) == 0)
|
|
|
|
|
return extract_unsigned_integer (buf, 4, byte_order_for_code);
|
|
|
|
|
}
|
2018-07-25 10:43:22 +01:00
|
|
|
|
2022-09-13 14:19:26 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2018-07-25 10:43:22 +01:00
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
csky_stub_unwind_sniffer (const struct frame_unwind *self,
|
2022-07-25 14:06:35 -03:00
|
|
|
frame_info_ptr this_frame,
|
2022-09-13 14:19:26 +08:00
|
|
|
void **this_prologue_cache)
|
2018-07-25 10:43:22 +01:00
|
|
|
{
|
2022-09-13 14:19:26 +08:00
|
|
|
CORE_ADDR addr_in_block, pc;
|
|
|
|
|
gdb_byte dummy[4];
|
|
|
|
|
const char *name;
|
|
|
|
|
CORE_ADDR start_addr;
|
2018-07-25 10:43:22 +01:00
|
|
|
|
2022-09-13 14:19:26 +08:00
|
|
|
/* Get pc */
|
2018-07-25 10:43:22 +01:00
|
|
|
addr_in_block = get_frame_address_in_block (this_frame);
|
2022-09-13 14:19:26 +08:00
|
|
|
pc = get_frame_pc (this_frame);
|
2018-07-25 10:43:22 +01:00
|
|
|
|
2022-09-13 14:19:26 +08:00
|
|
|
if (in_plt_section (addr_in_block)
|
|
|
|
|
|| target_read_memory (pc, dummy, 4) != 0)
|
2018-07-25 10:43:22 +01:00
|
|
|
return 1;
|
|
|
|
|
|
2022-09-13 14:19:26 +08:00
|
|
|
/* Find the starting address and name of the function containing the PC. */
|
|
|
|
|
if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
|
|
|
|
|
{
|
|
|
|
|
start_addr = csky_check_long_branch (this_frame, pc);
|
|
|
|
|
/* if not long branch, return 0. */
|
|
|
|
|
if (start_addr != 0)
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-25 10:43:22 +01:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct csky_unwind_cache *
|
2022-07-25 14:06:35 -03:00
|
|
|
csky_make_stub_cache (frame_info_ptr this_frame)
|
2018-07-25 10:43:22 +01:00
|
|
|
{
|
|
|
|
|
struct csky_unwind_cache *cache;
|
|
|
|
|
|
|
|
|
|
cache = FRAME_OBSTACK_ZALLOC (struct csky_unwind_cache);
|
|
|
|
|
cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
|
|
|
|
|
cache->prev_sp = get_frame_register_unsigned (this_frame, CSKY_SP_REGNUM);
|
|
|
|
|
|
|
|
|
|
return cache;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2022-07-25 14:06:35 -03:00
|
|
|
csky_stub_this_id (frame_info_ptr this_frame,
|
2018-07-25 10:43:22 +01:00
|
|
|
void **this_cache,
|
|
|
|
|
struct frame_id *this_id)
|
|
|
|
|
{
|
|
|
|
|
struct csky_unwind_cache *cache;
|
|
|
|
|
|
|
|
|
|
if (*this_cache == NULL)
|
|
|
|
|
*this_cache = csky_make_stub_cache (this_frame);
|
|
|
|
|
cache = (struct csky_unwind_cache *) *this_cache;
|
|
|
|
|
|
|
|
|
|
/* Our frame ID for a stub frame is the current SP and LR. */
|
|
|
|
|
*this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct value *
|
2022-07-25 14:06:35 -03:00
|
|
|
csky_stub_prev_register (frame_info_ptr this_frame,
|
2018-07-25 10:43:22 +01:00
|
|
|
void **this_cache,
|
|
|
|
|
int prev_regnum)
|
|
|
|
|
{
|
|
|
|
|
struct csky_unwind_cache *cache;
|
|
|
|
|
|
|
|
|
|
if (*this_cache == NULL)
|
|
|
|
|
*this_cache = csky_make_stub_cache (this_frame);
|
|
|
|
|
cache = (struct csky_unwind_cache *) *this_cache;
|
|
|
|
|
|
|
|
|
|
/* If we are asked to unwind the PC, then return the LR. */
|
|
|
|
|
if (prev_regnum == CSKY_PC_REGNUM)
|
|
|
|
|
{
|
|
|
|
|
CORE_ADDR lr;
|
|
|
|
|
|
|
|
|
|
lr = frame_unwind_register_unsigned (this_frame, CSKY_LR_REGNUM);
|
|
|
|
|
return frame_unwind_got_constant (this_frame, prev_regnum, lr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (prev_regnum == CSKY_SP_REGNUM)
|
|
|
|
|
return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
|
|
|
|
|
|
|
|
|
|
return trad_frame_get_prev_register (this_frame, cache->saved_regs,
|
|
|
|
|
prev_regnum);
|
|
|
|
|
}
|
|
|
|
|
|
gdb: make some variables static
I'm trying to enable clang's -Wmissing-variable-declarations warning.
This patch fixes all the obvious spots where we can simply add "static"
(at least, found when building on x86-64 Linux).
gdb/ChangeLog:
* aarch64-linux-tdep.c (aarch64_linux_record_tdep): Make static.
* aarch64-tdep.c (tdesc_aarch64_list, aarch64_prologue_unwind,
aarch64_stub_unwind, aarch64_normal_base, ): Make static.
* arm-linux-tdep.c (arm_prologue_unwind): Make static.
* arm-tdep.c (struct frame_unwind): Make static.
* auto-load.c (auto_load_safe_path_vec): Make static.
* csky-tdep.c (csky_stub_unwind): Make static.
* gdbarch.c (gdbarch_data_registry): Make static.
* gnu-v2-abi.c (gnu_v2_abi_ops): Make static.
* i386-netbsd-tdep.c (i386nbsd_mc_reg_offset): Make static.
* i386-tdep.c (i386_frame_setup_skip_insns,
i386_tramp_chain_in_reg_insns, i386_tramp_chain_on_stack_insns):
Make static.
* infrun.c (observer_mode): Make static.
* linux-nat.c (sigchld_action): Make static.
* linux-thread-db.c (thread_db_list): Make static.
* maint-test-options.c (maintenance_test_options_list):
* mep-tdep.c (mep_csr_registers): Make static.
* mi/mi-cmds.c (struct mi_cmd_stats): Remove struct type name.
(stats): Make static.
* nat/linux-osdata.c (struct osdata_type): Make static.
* ppc-netbsd-tdep.c (ppcnbsd_reg_offsets): Make static.
* progspace.c (last_program_space_num): Make static.
* python/py-param.c (struct parm_constant): Remove struct type
name.
(parm_constants): Make static.
* python/py-record-btrace.c (btpy_list_methods): Make static.
* python/py-record.c (recpy_gap_type): Make static.
* record.c (record_goto_cmdlist): Make static.
* regcache.c (regcache_descr_handle): Make static.
* registry.h (DEFINE_REGISTRY): Make definition static.
* symmisc.c (std_in, std_out, std_err): Make static.
* top.c (previous_saved_command_line): Make static.
* tracepoint.c (trace_user, trace_notes, trace_stop_notes): Make
static.
* unittests/command-def-selftests.c (nr_duplicates,
nr_invalid_prefixcmd, lists): Make static.
* unittests/observable-selftests.c (test_notification): Make
static.
* unittests/optional/assignment/1.cc (counter): Make static.
* unittests/optional/assignment/2.cc (counter): Make static.
* unittests/optional/assignment/3.cc (counter): Make static.
* unittests/optional/assignment/4.cc (counter): Make static.
* unittests/optional/assignment/5.cc (counter): Make static.
* unittests/optional/assignment/6.cc (counter): Make static.
gdbserver/ChangeLog:
* ax.cc (bytecode_address_table): Make static.
* debug.cc (debug_file): Make static.
* linux-low.cc (stopping_threads): Make static.
(step_over_bkpt): Make static.
* linux-x86-low.cc (amd64_emit_ops, i386_emit_ops): Make static.
* tracepoint.cc (stop_tracing_bkpt, flush_trace_buffer_bkpt,
alloced_trace_state_variables, trace_buffer_ctrl,
tracing_start_time, tracing_stop_time, tracing_user_name,
tracing_notes, tracing_stop_note): Make static.
Change-Id: Ic1d8034723b7802502bda23770893be2338ab020
2021-01-20 20:55:05 -05:00
|
|
|
static frame_unwind csky_stub_unwind = {
|
2021-06-29 12:05:03 -04:00
|
|
|
"csky stub",
|
2018-07-25 10:43:22 +01:00
|
|
|
NORMAL_FRAME,
|
|
|
|
|
default_frame_unwind_stop_reason,
|
|
|
|
|
csky_stub_this_id,
|
|
|
|
|
csky_stub_prev_register,
|
|
|
|
|
NULL,
|
|
|
|
|
csky_stub_unwind_sniffer
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Implement the this_base, this_locals, and this_args hooks
|
|
|
|
|
for the normal unwinder. */
|
|
|
|
|
|
|
|
|
|
static CORE_ADDR
|
2022-07-25 14:06:35 -03:00
|
|
|
csky_frame_base_address (frame_info_ptr this_frame, void **this_cache)
|
2018-07-25 10:43:22 +01:00
|
|
|
{
|
|
|
|
|
struct csky_unwind_cache *cache;
|
|
|
|
|
|
|
|
|
|
if (*this_cache == NULL)
|
|
|
|
|
*this_cache = csky_frame_unwind_cache (this_frame);
|
|
|
|
|
cache = (struct csky_unwind_cache *) *this_cache;
|
|
|
|
|
|
|
|
|
|
return cache->prev_sp - cache->framesize;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct frame_base csky_frame_base = {
|
|
|
|
|
&csky_unwind_cache,
|
|
|
|
|
csky_frame_base_address,
|
|
|
|
|
csky_frame_base_address,
|
|
|
|
|
csky_frame_base_address
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Initialize register access method. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
csky_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
|
|
|
|
|
struct dwarf2_frame_state_reg *reg,
|
2022-07-25 14:06:35 -03:00
|
|
|
frame_info_ptr this_frame)
|
2018-07-25 10:43:22 +01:00
|
|
|
{
|
|
|
|
|
if (regnum == gdbarch_pc_regnum (gdbarch))
|
|
|
|
|
reg->how = DWARF2_FRAME_REG_RA;
|
|
|
|
|
else if (regnum == gdbarch_sp_regnum (gdbarch))
|
|
|
|
|
reg->how = DWARF2_FRAME_REG_CFA;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Create csky register groups. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
csky_init_reggroup ()
|
|
|
|
|
{
|
|
|
|
|
cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
|
|
|
|
|
fr_reggroup = reggroup_new ("fr", USER_REGGROUP);
|
|
|
|
|
vr_reggroup = reggroup_new ("vr", USER_REGGROUP);
|
|
|
|
|
mmu_reggroup = reggroup_new ("mmu", USER_REGGROUP);
|
|
|
|
|
prof_reggroup = reggroup_new ("profiling", USER_REGGROUP);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Add register groups into reggroup list. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
csky_add_reggroups (struct gdbarch *gdbarch)
|
|
|
|
|
{
|
|
|
|
|
reggroup_add (gdbarch, cr_reggroup);
|
|
|
|
|
reggroup_add (gdbarch, fr_reggroup);
|
|
|
|
|
reggroup_add (gdbarch, vr_reggroup);
|
|
|
|
|
reggroup_add (gdbarch, mmu_reggroup);
|
|
|
|
|
reggroup_add (gdbarch, prof_reggroup);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return the groups that a CSKY register can be categorised into. */
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
csky_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
|
2022-03-31 12:36:06 +01:00
|
|
|
const struct reggroup *reggroup)
|
2018-07-25 10:43:22 +01:00
|
|
|
{
|
|
|
|
|
int raw_p;
|
|
|
|
|
|
2022-08-31 15:42:43 +01:00
|
|
|
if (gdbarch_register_name (gdbarch, regnum)[0] == '\0')
|
2018-07-25 10:43:22 +01:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
if (reggroup == all_reggroup)
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
raw_p = regnum < gdbarch_num_regs (gdbarch);
|
|
|
|
|
if (reggroup == save_reggroup || reggroup == restore_reggroup)
|
|
|
|
|
return raw_p;
|
|
|
|
|
|
2022-07-22 10:33:14 +08:00
|
|
|
if ((((regnum >= CSKY_R0_REGNUM) && (regnum <= CSKY_R0_REGNUM + 31))
|
|
|
|
|
|| (regnum == CSKY_PC_REGNUM)
|
|
|
|
|
|| (regnum == CSKY_EPC_REGNUM)
|
|
|
|
|
|| (regnum == CSKY_CR0_REGNUM)
|
|
|
|
|
|| (regnum == CSKY_EPSR_REGNUM))
|
2018-07-25 10:43:22 +01:00
|
|
|
&& (reggroup == general_reggroup))
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
if (((regnum == CSKY_PC_REGNUM)
|
|
|
|
|
|| ((regnum >= CSKY_CR0_REGNUM)
|
|
|
|
|
&& (regnum <= CSKY_CR0_REGNUM + 30)))
|
|
|
|
|
&& (reggroup == cr_reggroup))
|
|
|
|
|
return 2;
|
|
|
|
|
|
|
|
|
|
if ((((regnum >= CSKY_VR0_REGNUM) && (regnum <= CSKY_VR0_REGNUM + 15))
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
|| ((regnum >= CSKY_FCR_REGNUM)
|
|
|
|
|
&& (regnum <= CSKY_FCR_REGNUM + 2)))
|
2018-07-25 10:43:22 +01:00
|
|
|
&& (reggroup == vr_reggroup))
|
|
|
|
|
return 3;
|
|
|
|
|
|
|
|
|
|
if (((regnum >= CSKY_MMU_REGNUM) && (regnum <= CSKY_MMU_REGNUM + 8))
|
|
|
|
|
&& (reggroup == mmu_reggroup))
|
|
|
|
|
return 4;
|
|
|
|
|
|
|
|
|
|
if (((regnum >= CSKY_PROFCR_REGNUM)
|
|
|
|
|
&& (regnum <= CSKY_PROFCR_REGNUM + 48))
|
|
|
|
|
&& (reggroup == prof_reggroup))
|
|
|
|
|
return 5;
|
|
|
|
|
|
|
|
|
|
if ((((regnum >= CSKY_FR0_REGNUM) && (regnum <= CSKY_FR0_REGNUM + 15))
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
|| ((regnum >= CSKY_FCR_REGNUM) && (regnum <= CSKY_FCR_REGNUM + 2)))
|
2018-07-25 10:43:22 +01:00
|
|
|
&& (reggroup == fr_reggroup))
|
|
|
|
|
return 6;
|
|
|
|
|
|
2022-07-22 10:33:14 +08:00
|
|
|
if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
|
|
|
|
|
{
|
|
|
|
|
if (tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup) > 0)
|
2023-03-09 14:56:09 -05:00
|
|
|
return 7;
|
2022-07-22 10:33:14 +08:00
|
|
|
}
|
|
|
|
|
|
2018-07-25 10:43:22 +01:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implement the dwarf2_reg_to_regnum gdbarch method. */
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
csky_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg)
|
|
|
|
|
{
|
2022-07-12 09:54:58 +08:00
|
|
|
/* For GPRs. */
|
2022-07-22 10:33:14 +08:00
|
|
|
if (dw_reg >= CSKY_R0_REGNUM && dw_reg <= CSKY_R0_REGNUM + 31)
|
2022-07-12 09:54:58 +08:00
|
|
|
return dw_reg;
|
|
|
|
|
|
|
|
|
|
/* For Hi, Lo, PC. */
|
2022-07-22 10:33:14 +08:00
|
|
|
if (dw_reg == CSKY_HI_REGNUM || dw_reg == CSKY_LO_REGNUM
|
|
|
|
|
|| dw_reg == CSKY_PC_REGNUM)
|
2022-07-12 09:54:58 +08:00
|
|
|
return dw_reg;
|
|
|
|
|
|
|
|
|
|
/* For Float and Vector pseudo registers. */
|
2022-07-22 10:33:14 +08:00
|
|
|
if (dw_reg >= FV_PSEUDO_REGNO_FIRST && dw_reg <= FV_PSEUDO_REGNO_LAST)
|
2022-07-12 09:54:58 +08:00
|
|
|
{
|
|
|
|
|
char name_buf[4];
|
|
|
|
|
|
|
|
|
|
xsnprintf (name_buf, sizeof (name_buf), "s%d",
|
2023-03-09 14:56:09 -05:00
|
|
|
dw_reg - FV_PSEUDO_REGNO_FIRST);
|
2022-07-12 09:54:58 +08:00
|
|
|
return user_reg_map_name_to_regnum (gdbarch, name_buf,
|
2023-03-09 14:56:09 -05:00
|
|
|
strlen (name_buf));
|
2022-07-12 09:54:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Others, unknown. */
|
|
|
|
|
return -1;
|
2018-07-25 10:43:22 +01:00
|
|
|
}
|
|
|
|
|
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
/* Check whether xml has discribled the essential regs. */
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
static int
|
|
|
|
|
csky_essential_reg_check (const struct csky_supported_tdesc_register *reg)
|
|
|
|
|
{
|
|
|
|
|
if ((strcmp (reg->name , "pc") == 0)
|
|
|
|
|
&& (reg->num == CSKY_PC_REGNUM))
|
|
|
|
|
return CSKY_TDESC_REGS_PC_NUMBERED;
|
|
|
|
|
else if ((strcmp (reg->name , "r14") == 0)
|
|
|
|
|
&& (reg->num == CSKY_SP_REGNUM))
|
|
|
|
|
return CSKY_TDESC_REGS_SP_NUMBERED;
|
|
|
|
|
else if ((strcmp (reg->name , "r15") == 0)
|
|
|
|
|
&& (reg->num == CSKY_LR_REGNUM))
|
|
|
|
|
return CSKY_TDESC_REGS_LR_NUMBERED;
|
|
|
|
|
else
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
/* Check whether xml has discribled the fr0~fr15 regs. */
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
csky_fr0_fr15_reg_check (const struct csky_supported_tdesc_register *reg) {
|
|
|
|
|
int i = 0;
|
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
|
{
|
|
|
|
|
if ((strcmp (reg->name, csky_supported_fpu_regs[i].name) == 0)
|
2023-03-09 14:56:09 -05:00
|
|
|
&& (csky_supported_fpu_regs[i].num == reg->num))
|
|
|
|
|
return (1 << i);
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Check whether xml has discribled the fr16~fr31 regs. */
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
csky_fr16_fr31_reg_check (const struct csky_supported_tdesc_register *reg) {
|
|
|
|
|
int i = 0;
|
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
|
{
|
|
|
|
|
if ((strcmp (reg->name, csky_supported_fpu_regs[i + 16].name) == 0)
|
2023-03-09 14:56:09 -05:00
|
|
|
&& (csky_supported_fpu_regs[i + 16].num == reg->num))
|
|
|
|
|
return (1 << i);
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Check whether xml has discribled the vr0~vr15 regs. */
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
csky_vr0_vr15_reg_check (const struct csky_supported_tdesc_register *reg) {
|
|
|
|
|
int i = 0;
|
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
|
{
|
|
|
|
|
if ((strcmp (reg->name, csky_supported_fpu_regs[i + 32].name) == 0)
|
2023-03-09 14:56:09 -05:00
|
|
|
&& (csky_supported_fpu_regs[i + 32].num == reg->num))
|
|
|
|
|
return (1 << i);
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Return pseudo reg's name. */
|
|
|
|
|
|
|
|
|
|
static const char *
|
|
|
|
|
csky_pseudo_register_name (struct gdbarch *gdbarch, int regno)
|
|
|
|
|
{
|
|
|
|
|
int num_regs = gdbarch_num_regs (gdbarch);
|
|
|
|
|
csky_gdbarch_tdep *tdep
|
gdb: move the type cast into gdbarch_tdep
I built GDB for all targets on a x86-64/GNU-Linux system, and
then (accidentally) passed GDB a RISC-V binary, and asked GDB to "run"
the binary on the native target. I got this error:
(gdb) show architecture
The target architecture is set to "auto" (currently "i386").
(gdb) file /tmp/hello.rv32.exe
Reading symbols from /tmp/hello.rv32.exe...
(gdb) show architecture
The target architecture is set to "auto" (currently "riscv:rv32").
(gdb) run
Starting program: /tmp/hello.rv32.exe
../../src/gdb/i387-tdep.c:596: internal-error: i387_supply_fxsave: Assertion `tdep->st0_regnum >= I386_ST0_REGNUM' failed.
What's going on here is this; initially the architecture is i386, this
is based on the default architecture, which is set based on the native
target. After loading the RISC-V executable the architecture of the
current inferior is updated based on the architecture of the
executable.
When we "run", GDB does a fork & exec, with the inferior being
controlled through ptrace. GDB sees an initial stop from the inferior
as soon as the inferior comes to life. In response to this stop GDB
ends up calling save_stop_reason (linux-nat.c), which ends up trying
to read register from the inferior, to do this we end up calling
target_ops::fetch_registers, which, for the x86-64 native target,
calls amd64_linux_nat_target::fetch_registers.
After this I eventually end up in i387_supply_fxsave, different x86
based targets will end in different functions to fetch registers, but
it doesn't really matter which function we end up in, the problem is
this line, which is repeated in many places:
i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
The problem here is that the ARCH in this line comes from the current
inferior, which, as we discussed above, will be a RISC-V gdbarch, the
tdep field will actually be of type riscv_gdbarch_tdep, not
i386_gdbarch_tdep. After this cast we are relying on undefined
behaviour, in my case I happen to trigger an assert, but this might
not always be the case.
The thing I tried that exposed this problem was of course, trying to
start an executable of the wrong architecture on a native target. I
don't think that the correct solution for this problem is to detect,
at the point of cast, that the gdbarch_tdep object is of the wrong
type, but, I did wonder, is there a way that we could protect
ourselves from incorrectly casting the gdbarch_tdep object?
I think that there is something we can do here, and this commit is the
first step in that direction, though no actual check is added by this
commit.
This commit can be split into two parts:
(1) In gdbarch.h and arch-utils.c. In these files I have modified
gdbarch_tdep (the function) so that it now takes a template argument,
like this:
template<typename TDepType>
static inline TDepType *
gdbarch_tdep (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep_1 (gdbarch);
return static_cast<TDepType *> (tdep);
}
After this change we are no better protected, but the cast is now
done within the gdbarch_tdep function rather than at the call sites,
this leads to the second, much larger change in this commit,
(2) Everywhere gdbarch_tdep is called, we make changes like this:
- i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
+ i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
There should be no functional change after this commit.
In the next commit I will build on this change to add an assertion in
gdbarch_tdep that checks we are casting to the correct type.
2022-05-19 13:20:17 +01:00
|
|
|
= gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
|
|
|
|
|
regno -= num_regs;
|
|
|
|
|
|
|
|
|
|
if (tdep->fv_pseudo_registers_count)
|
|
|
|
|
{
|
|
|
|
|
static const char *const fv_pseudo_names[] = {
|
2023-03-09 14:56:09 -05:00
|
|
|
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
|
|
|
|
|
"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
|
|
|
|
|
"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
|
|
|
|
|
"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
|
|
|
|
|
"s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
|
|
|
|
|
"s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
|
|
|
|
|
"s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
|
|
|
|
|
"s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
|
|
|
|
|
"s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
|
|
|
|
|
"s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
|
|
|
|
|
"s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
|
|
|
|
|
"s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
|
|
|
|
|
"s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
|
|
|
|
|
"s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
|
|
|
|
|
"s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
|
|
|
|
|
"s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
if (regno < tdep->fv_pseudo_registers_count)
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
if ((regno < 64) && ((regno % 4) >= 2) && !tdep->has_vr0)
|
|
|
|
|
return "";
|
|
|
|
|
else if ((regno >= 64) && ((regno % 4) >= 2))
|
|
|
|
|
return "";
|
|
|
|
|
else
|
|
|
|
|
return fv_pseudo_names[regno];
|
|
|
|
|
}
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
}
|
|
|
|
|
|
2022-09-01 15:39:59 +01:00
|
|
|
return "";
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Read for csky pseudo regs. */
|
|
|
|
|
|
|
|
|
|
static enum register_status
|
|
|
|
|
csky_pseudo_register_read (struct gdbarch *gdbarch,
|
2023-03-09 14:56:09 -05:00
|
|
|
struct readable_regcache *regcache,
|
|
|
|
|
int regnum, gdb_byte *buf)
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
{
|
|
|
|
|
int num_regs = gdbarch_num_regs (gdbarch);
|
|
|
|
|
csky_gdbarch_tdep *tdep
|
gdb: move the type cast into gdbarch_tdep
I built GDB for all targets on a x86-64/GNU-Linux system, and
then (accidentally) passed GDB a RISC-V binary, and asked GDB to "run"
the binary on the native target. I got this error:
(gdb) show architecture
The target architecture is set to "auto" (currently "i386").
(gdb) file /tmp/hello.rv32.exe
Reading symbols from /tmp/hello.rv32.exe...
(gdb) show architecture
The target architecture is set to "auto" (currently "riscv:rv32").
(gdb) run
Starting program: /tmp/hello.rv32.exe
../../src/gdb/i387-tdep.c:596: internal-error: i387_supply_fxsave: Assertion `tdep->st0_regnum >= I386_ST0_REGNUM' failed.
What's going on here is this; initially the architecture is i386, this
is based on the default architecture, which is set based on the native
target. After loading the RISC-V executable the architecture of the
current inferior is updated based on the architecture of the
executable.
When we "run", GDB does a fork & exec, with the inferior being
controlled through ptrace. GDB sees an initial stop from the inferior
as soon as the inferior comes to life. In response to this stop GDB
ends up calling save_stop_reason (linux-nat.c), which ends up trying
to read register from the inferior, to do this we end up calling
target_ops::fetch_registers, which, for the x86-64 native target,
calls amd64_linux_nat_target::fetch_registers.
After this I eventually end up in i387_supply_fxsave, different x86
based targets will end in different functions to fetch registers, but
it doesn't really matter which function we end up in, the problem is
this line, which is repeated in many places:
i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
The problem here is that the ARCH in this line comes from the current
inferior, which, as we discussed above, will be a RISC-V gdbarch, the
tdep field will actually be of type riscv_gdbarch_tdep, not
i386_gdbarch_tdep. After this cast we are relying on undefined
behaviour, in my case I happen to trigger an assert, but this might
not always be the case.
The thing I tried that exposed this problem was of course, trying to
start an executable of the wrong architecture on a native target. I
don't think that the correct solution for this problem is to detect,
at the point of cast, that the gdbarch_tdep object is of the wrong
type, but, I did wonder, is there a way that we could protect
ourselves from incorrectly casting the gdbarch_tdep object?
I think that there is something we can do here, and this commit is the
first step in that direction, though no actual check is added by this
commit.
This commit can be split into two parts:
(1) In gdbarch.h and arch-utils.c. In these files I have modified
gdbarch_tdep (the function) so that it now takes a template argument,
like this:
template<typename TDepType>
static inline TDepType *
gdbarch_tdep (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep_1 (gdbarch);
return static_cast<TDepType *> (tdep);
}
After this change we are no better protected, but the cast is now
done within the gdbarch_tdep function rather than at the call sites,
this leads to the second, much larger change in this commit,
(2) Everywhere gdbarch_tdep is called, we make changes like this:
- i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
+ i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
There should be no functional change after this commit.
In the next commit I will build on this change to add an assertion in
gdbarch_tdep that checks we are casting to the correct type.
2022-05-19 13:20:17 +01:00
|
|
|
= gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
|
|
|
|
|
regnum -= num_regs;
|
|
|
|
|
|
|
|
|
|
if (regnum < tdep->fv_pseudo_registers_count)
|
|
|
|
|
{
|
|
|
|
|
enum register_status status;
|
|
|
|
|
int gdb_regnum = 0;
|
|
|
|
|
int offset = 0;
|
|
|
|
|
gdb_byte reg_buf[16];
|
|
|
|
|
|
2023-06-05 12:53:15 +02:00
|
|
|
/* Ensure getting s0~s63 from vrx if tdep->has_vr0 is true. */
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
if (tdep->has_vr0)
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
if (regnum < 64)
|
|
|
|
|
{
|
|
|
|
|
gdb_regnum = CSKY_VR0_REGNUM + (regnum / 4);
|
|
|
|
|
offset = (regnum % 4) * 4;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
gdb_regnum = CSKY_FR16_REGNUM + ((regnum - 64) / 4);
|
|
|
|
|
if ((regnum % 4) >= 2)
|
|
|
|
|
return REG_UNAVAILABLE;
|
|
|
|
|
offset = (regnum % 2) * 4;
|
|
|
|
|
}
|
|
|
|
|
}
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
else
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
gdb_regnum = CSKY_FR0_REGNUM + (regnum / 4);
|
|
|
|
|
if ((regnum % 4) >= 2)
|
|
|
|
|
return REG_UNAVAILABLE;
|
|
|
|
|
offset = (regnum % 2) * 4;
|
|
|
|
|
}
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
|
|
|
|
|
status = regcache->raw_read (gdb_regnum, reg_buf);
|
|
|
|
|
if (status == REG_VALID)
|
2023-03-09 14:56:09 -05:00
|
|
|
memcpy (buf, reg_buf + offset, 4);
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
return status;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return REG_UNKNOWN;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Write for csky pseudo regs. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
csky_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
|
2023-03-09 14:56:09 -05:00
|
|
|
int regnum, const gdb_byte *buf)
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
{
|
|
|
|
|
int num_regs = gdbarch_num_regs (gdbarch);
|
|
|
|
|
csky_gdbarch_tdep *tdep
|
gdb: move the type cast into gdbarch_tdep
I built GDB for all targets on a x86-64/GNU-Linux system, and
then (accidentally) passed GDB a RISC-V binary, and asked GDB to "run"
the binary on the native target. I got this error:
(gdb) show architecture
The target architecture is set to "auto" (currently "i386").
(gdb) file /tmp/hello.rv32.exe
Reading symbols from /tmp/hello.rv32.exe...
(gdb) show architecture
The target architecture is set to "auto" (currently "riscv:rv32").
(gdb) run
Starting program: /tmp/hello.rv32.exe
../../src/gdb/i387-tdep.c:596: internal-error: i387_supply_fxsave: Assertion `tdep->st0_regnum >= I386_ST0_REGNUM' failed.
What's going on here is this; initially the architecture is i386, this
is based on the default architecture, which is set based on the native
target. After loading the RISC-V executable the architecture of the
current inferior is updated based on the architecture of the
executable.
When we "run", GDB does a fork & exec, with the inferior being
controlled through ptrace. GDB sees an initial stop from the inferior
as soon as the inferior comes to life. In response to this stop GDB
ends up calling save_stop_reason (linux-nat.c), which ends up trying
to read register from the inferior, to do this we end up calling
target_ops::fetch_registers, which, for the x86-64 native target,
calls amd64_linux_nat_target::fetch_registers.
After this I eventually end up in i387_supply_fxsave, different x86
based targets will end in different functions to fetch registers, but
it doesn't really matter which function we end up in, the problem is
this line, which is repeated in many places:
i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
The problem here is that the ARCH in this line comes from the current
inferior, which, as we discussed above, will be a RISC-V gdbarch, the
tdep field will actually be of type riscv_gdbarch_tdep, not
i386_gdbarch_tdep. After this cast we are relying on undefined
behaviour, in my case I happen to trigger an assert, but this might
not always be the case.
The thing I tried that exposed this problem was of course, trying to
start an executable of the wrong architecture on a native target. I
don't think that the correct solution for this problem is to detect,
at the point of cast, that the gdbarch_tdep object is of the wrong
type, but, I did wonder, is there a way that we could protect
ourselves from incorrectly casting the gdbarch_tdep object?
I think that there is something we can do here, and this commit is the
first step in that direction, though no actual check is added by this
commit.
This commit can be split into two parts:
(1) In gdbarch.h and arch-utils.c. In these files I have modified
gdbarch_tdep (the function) so that it now takes a template argument,
like this:
template<typename TDepType>
static inline TDepType *
gdbarch_tdep (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep_1 (gdbarch);
return static_cast<TDepType *> (tdep);
}
After this change we are no better protected, but the cast is now
done within the gdbarch_tdep function rather than at the call sites,
this leads to the second, much larger change in this commit,
(2) Everywhere gdbarch_tdep is called, we make changes like this:
- i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
+ i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
There should be no functional change after this commit.
In the next commit I will build on this change to add an assertion in
gdbarch_tdep that checks we are casting to the correct type.
2022-05-19 13:20:17 +01:00
|
|
|
= gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
|
|
|
|
|
regnum -= num_regs;
|
|
|
|
|
|
|
|
|
|
if (regnum < tdep->fv_pseudo_registers_count)
|
|
|
|
|
{
|
|
|
|
|
gdb_byte reg_buf[16];
|
|
|
|
|
int gdb_regnum = 0;
|
|
|
|
|
int offset = 0;
|
|
|
|
|
|
|
|
|
|
if (tdep->has_vr0)
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
if (regnum < 64)
|
|
|
|
|
{
|
|
|
|
|
gdb_regnum = CSKY_VR0_REGNUM + (regnum / 4);
|
|
|
|
|
offset = (regnum % 4) * 4;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
gdb_regnum = CSKY_FR16_REGNUM + ((regnum - 64) / 4);
|
|
|
|
|
if ((regnum % 4) >= 2)
|
|
|
|
|
return;
|
|
|
|
|
offset = (regnum % 2) * 4;
|
|
|
|
|
}
|
|
|
|
|
}
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
else
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
gdb_regnum = CSKY_FR0_REGNUM + (regnum / 4);
|
|
|
|
|
if ((regnum % 4) >= 2)
|
|
|
|
|
return;
|
|
|
|
|
offset = (regnum % 2) * 4;
|
|
|
|
|
}
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
|
|
|
|
|
regcache->raw_read (gdb_regnum, reg_buf);
|
|
|
|
|
memcpy (reg_buf + offset, buf, 4);
|
|
|
|
|
regcache->raw_write (gdb_regnum, reg_buf);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-25 10:43:22 +01:00
|
|
|
/* Initialize the current architecture based on INFO. If possible,
|
|
|
|
|
re-use an architecture from ARCHES, which is a list of
|
|
|
|
|
architectures already created during this debugging session.
|
|
|
|
|
|
|
|
|
|
Called at program startup, when reading a core file, and when
|
|
|
|
|
reading a binary file. */
|
|
|
|
|
|
|
|
|
|
static struct gdbarch *
|
|
|
|
|
csky_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
|
|
|
|
{
|
2022-06-01 14:46:01 +08:00
|
|
|
/* Analyze info.abfd. */
|
|
|
|
|
unsigned int fpu_abi = 0;
|
|
|
|
|
unsigned int vdsp_version = 0;
|
|
|
|
|
unsigned int fpu_hardfp = 0;
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
/* Analyze info.target_desc */
|
|
|
|
|
int num_regs = 0;
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
int has_fr0 = 0;
|
|
|
|
|
int has_fr16 = 0;
|
|
|
|
|
int has_vr0 = 0;
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
tdesc_arch_data_up tdesc_data;
|
|
|
|
|
|
|
|
|
|
if (tdesc_has_registers (info.target_desc))
|
|
|
|
|
{
|
|
|
|
|
int valid_p = 0;
|
|
|
|
|
int numbered = 0;
|
|
|
|
|
int index = 0;
|
|
|
|
|
int i = 0;
|
|
|
|
|
int feature_names_count = ARRAY_SIZE (csky_supported_tdesc_feature_names);
|
|
|
|
|
int support_tdesc_regs_count
|
2023-03-09 14:56:09 -05:00
|
|
|
= csky_get_supported_tdesc_registers_count();
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
const struct csky_supported_tdesc_register *tdesc_reg;
|
|
|
|
|
const struct tdesc_feature *feature;
|
|
|
|
|
|
|
|
|
|
tdesc_data = tdesc_data_alloc ();
|
|
|
|
|
for (index = 0; index < feature_names_count; index ++)
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
feature = tdesc_find_feature (info.target_desc,
|
|
|
|
|
csky_supported_tdesc_feature_names[index]);
|
|
|
|
|
if (feature != NULL)
|
|
|
|
|
{
|
|
|
|
|
for (i = 0; i < support_tdesc_regs_count; i++)
|
|
|
|
|
{
|
|
|
|
|
tdesc_reg = csky_get_supported_register_by_index (i);
|
|
|
|
|
if (!tdesc_reg)
|
|
|
|
|
break;
|
|
|
|
|
numbered = tdesc_numbered_register (feature, tdesc_data.get(),
|
|
|
|
|
tdesc_reg->num,
|
|
|
|
|
tdesc_reg->name);
|
|
|
|
|
if (numbered) {
|
|
|
|
|
valid_p |= csky_essential_reg_check (tdesc_reg);
|
|
|
|
|
has_fr0 |= csky_fr0_fr15_reg_check (tdesc_reg);
|
|
|
|
|
has_fr16 |= csky_fr16_fr31_reg_check (tdesc_reg);
|
|
|
|
|
has_vr0 |= csky_vr0_vr15_reg_check (tdesc_reg);
|
|
|
|
|
if (num_regs < tdesc_reg->num)
|
|
|
|
|
num_regs = tdesc_reg->num;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
if (valid_p != CSKY_TDESC_REGS_ESSENTIAL_VALUE)
|
2023-03-09 14:56:09 -05:00
|
|
|
return NULL;
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
}
|
2022-06-01 14:46:01 +08:00
|
|
|
|
|
|
|
|
/* When the type of bfd file is srec(or any files are not elf),
|
|
|
|
|
the E_FLAGS will be not credible. */
|
|
|
|
|
if (info.abfd != NULL && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
|
|
|
|
|
{
|
|
|
|
|
/* Get FPU, VDSP build options. */
|
|
|
|
|
fpu_abi = bfd_elf_get_obj_attr_int (info.abfd,
|
2023-03-09 14:56:09 -05:00
|
|
|
OBJ_ATTR_PROC,
|
|
|
|
|
Tag_CSKY_FPU_ABI);
|
2022-06-01 14:46:01 +08:00
|
|
|
vdsp_version = bfd_elf_get_obj_attr_int (info.abfd,
|
2023-03-09 14:56:09 -05:00
|
|
|
OBJ_ATTR_PROC,
|
|
|
|
|
Tag_CSKY_VDSP_VERSION);
|
2022-06-01 14:46:01 +08:00
|
|
|
fpu_hardfp = bfd_elf_get_obj_attr_int (info.abfd,
|
2023-03-09 14:56:09 -05:00
|
|
|
OBJ_ATTR_PROC,
|
|
|
|
|
Tag_CSKY_FPU_HARDFP);
|
2022-06-01 14:46:01 +08:00
|
|
|
}
|
2018-07-25 10:43:22 +01:00
|
|
|
|
|
|
|
|
/* Find a candidate among the list of pre-declared architectures. */
|
2022-06-01 14:46:01 +08:00
|
|
|
for (arches = gdbarch_list_lookup_by_info (arches, &info);
|
|
|
|
|
arches != NULL;
|
|
|
|
|
arches = gdbarch_list_lookup_by_info (arches->next, &info))
|
|
|
|
|
{
|
|
|
|
|
csky_gdbarch_tdep *tdep
|
gdb: move the type cast into gdbarch_tdep
I built GDB for all targets on a x86-64/GNU-Linux system, and
then (accidentally) passed GDB a RISC-V binary, and asked GDB to "run"
the binary on the native target. I got this error:
(gdb) show architecture
The target architecture is set to "auto" (currently "i386").
(gdb) file /tmp/hello.rv32.exe
Reading symbols from /tmp/hello.rv32.exe...
(gdb) show architecture
The target architecture is set to "auto" (currently "riscv:rv32").
(gdb) run
Starting program: /tmp/hello.rv32.exe
../../src/gdb/i387-tdep.c:596: internal-error: i387_supply_fxsave: Assertion `tdep->st0_regnum >= I386_ST0_REGNUM' failed.
What's going on here is this; initially the architecture is i386, this
is based on the default architecture, which is set based on the native
target. After loading the RISC-V executable the architecture of the
current inferior is updated based on the architecture of the
executable.
When we "run", GDB does a fork & exec, with the inferior being
controlled through ptrace. GDB sees an initial stop from the inferior
as soon as the inferior comes to life. In response to this stop GDB
ends up calling save_stop_reason (linux-nat.c), which ends up trying
to read register from the inferior, to do this we end up calling
target_ops::fetch_registers, which, for the x86-64 native target,
calls amd64_linux_nat_target::fetch_registers.
After this I eventually end up in i387_supply_fxsave, different x86
based targets will end in different functions to fetch registers, but
it doesn't really matter which function we end up in, the problem is
this line, which is repeated in many places:
i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
The problem here is that the ARCH in this line comes from the current
inferior, which, as we discussed above, will be a RISC-V gdbarch, the
tdep field will actually be of type riscv_gdbarch_tdep, not
i386_gdbarch_tdep. After this cast we are relying on undefined
behaviour, in my case I happen to trigger an assert, but this might
not always be the case.
The thing I tried that exposed this problem was of course, trying to
start an executable of the wrong architecture on a native target. I
don't think that the correct solution for this problem is to detect,
at the point of cast, that the gdbarch_tdep object is of the wrong
type, but, I did wonder, is there a way that we could protect
ourselves from incorrectly casting the gdbarch_tdep object?
I think that there is something we can do here, and this commit is the
first step in that direction, though no actual check is added by this
commit.
This commit can be split into two parts:
(1) In gdbarch.h and arch-utils.c. In these files I have modified
gdbarch_tdep (the function) so that it now takes a template argument,
like this:
template<typename TDepType>
static inline TDepType *
gdbarch_tdep (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep_1 (gdbarch);
return static_cast<TDepType *> (tdep);
}
After this change we are no better protected, but the cast is now
done within the gdbarch_tdep function rather than at the call sites,
this leads to the second, much larger change in this commit,
(2) Everywhere gdbarch_tdep is called, we make changes like this:
- i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
+ i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
There should be no functional change after this commit.
In the next commit I will build on this change to add an assertion in
gdbarch_tdep that checks we are casting to the correct type.
2022-05-19 13:20:17 +01:00
|
|
|
= gdbarch_tdep<csky_gdbarch_tdep> (arches->gdbarch);
|
2022-06-01 14:46:01 +08:00
|
|
|
if (fpu_abi != tdep->fpu_abi)
|
2023-03-09 14:56:09 -05:00
|
|
|
continue;
|
2022-06-01 14:46:01 +08:00
|
|
|
if (vdsp_version != tdep->vdsp_version)
|
2023-03-09 14:56:09 -05:00
|
|
|
continue;
|
2022-06-01 14:46:01 +08:00
|
|
|
if (fpu_hardfp != tdep->fpu_hardfp)
|
2023-03-09 14:56:09 -05:00
|
|
|
continue;
|
2022-06-01 14:46:01 +08:00
|
|
|
|
|
|
|
|
/* Found a match. */
|
|
|
|
|
return arches->gdbarch;
|
|
|
|
|
}
|
2018-07-25 10:43:22 +01:00
|
|
|
|
|
|
|
|
/* None found, create a new architecture from the information
|
|
|
|
|
provided. */
|
gdb: make gdbarch_alloc take ownership of the tdep
It's currently not clear how the ownership of gdbarch_tdep objects
works. In fact, nothing ever takes ownership of it. This is mostly
fine because we never free gdbarch objects, and thus we never free
gdbarch_tdep objects. There is an exception to that however: when
initialization fails, we do free the gdbarch object that is not going to
be used, and we free the tdep too. Currently, i386 and s390 do it.
To make things clearer, change gdbarch_alloc so that it takes ownership
of the tdep. The tdep is thus automatically freed if the gdbarch is
freed.
Change all gdbarch initialization functions to pass a new gdbarch_tdep
object to gdbarch_alloc and then retrieve a non-owning reference from
the gdbarch object.
Before this patch, the xtensa architecture had a single global instance
of xtensa_gdbarch_tdep. Since we need to pass a dynamically allocated
gdbarch_tdep_base instance to gdbarch_alloc, remove this global
instance, and dynamically allocate one as needed, like we do for all
other architectures. Make the `rmap` array externally visible and
rename it to the less collision-prone `xtensa_rmap` name.
Change-Id: Id3d70493ef80ce4bdff701c57636f4c79ed8aea2
Approved-By: Andrew Burgess <aburgess@redhat.com>
2022-10-03 11:15:14 -04:00
|
|
|
gdbarch *gdbarch
|
|
|
|
|
= gdbarch_alloc (&info, gdbarch_tdep_up (new csky_gdbarch_tdep));
|
|
|
|
|
csky_gdbarch_tdep *tdep = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
|
|
|
|
|
|
2022-06-01 14:46:01 +08:00
|
|
|
tdep->fpu_abi = fpu_abi;
|
|
|
|
|
tdep->vdsp_version = vdsp_version;
|
|
|
|
|
tdep->fpu_hardfp = fpu_hardfp;
|
2018-07-25 10:43:22 +01:00
|
|
|
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
if (tdesc_data != NULL)
|
|
|
|
|
{
|
|
|
|
|
if ((has_vr0 == CSKY_FULL16_ONEHOT_VALUE)
|
2023-03-09 14:56:09 -05:00
|
|
|
&& (has_fr16 == CSKY_FULL16_ONEHOT_VALUE))
|
|
|
|
|
{
|
|
|
|
|
tdep->has_vr0 = 1;
|
|
|
|
|
tdep->fv_pseudo_registers_count = 128;
|
|
|
|
|
}
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
else if ((has_vr0 == CSKY_FULL16_ONEHOT_VALUE)
|
2023-03-09 14:56:09 -05:00
|
|
|
&& (has_fr16 != CSKY_FULL16_ONEHOT_VALUE))
|
|
|
|
|
{
|
|
|
|
|
tdep->has_vr0 = 1;
|
|
|
|
|
tdep->fv_pseudo_registers_count = 64;
|
|
|
|
|
}
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
else if ((has_fr0 == CSKY_FULL16_ONEHOT_VALUE)
|
2023-03-09 14:56:09 -05:00
|
|
|
&& (has_vr0 != CSKY_FULL16_ONEHOT_VALUE))
|
|
|
|
|
{
|
|
|
|
|
tdep->has_vr0 = 0;
|
|
|
|
|
tdep->fv_pseudo_registers_count = 64;
|
|
|
|
|
}
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
else
|
2023-03-09 14:56:09 -05:00
|
|
|
{
|
|
|
|
|
tdep->has_vr0 = 0;
|
|
|
|
|
tdep->fv_pseudo_registers_count = 0;
|
|
|
|
|
}
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
tdep->has_vr0 = 1;
|
|
|
|
|
tdep->fv_pseudo_registers_count = 64;
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-25 10:43:22 +01:00
|
|
|
/* Target data types. */
|
|
|
|
|
set_gdbarch_ptr_bit (gdbarch, 32);
|
|
|
|
|
set_gdbarch_addr_bit (gdbarch, 32);
|
|
|
|
|
set_gdbarch_short_bit (gdbarch, 16);
|
|
|
|
|
set_gdbarch_int_bit (gdbarch, 32);
|
|
|
|
|
set_gdbarch_long_bit (gdbarch, 32);
|
|
|
|
|
set_gdbarch_long_long_bit (gdbarch, 64);
|
|
|
|
|
set_gdbarch_float_bit (gdbarch, 32);
|
|
|
|
|
set_gdbarch_double_bit (gdbarch, 64);
|
|
|
|
|
set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
|
|
|
|
|
set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
|
|
|
|
|
|
|
|
|
|
/* Information about the target architecture. */
|
|
|
|
|
set_gdbarch_return_value (gdbarch, csky_return_value);
|
|
|
|
|
set_gdbarch_breakpoint_kind_from_pc (gdbarch, csky_breakpoint_kind_from_pc);
|
|
|
|
|
set_gdbarch_sw_breakpoint_from_kind (gdbarch, csky_sw_breakpoint_from_kind);
|
|
|
|
|
|
|
|
|
|
/* Register architecture. */
|
|
|
|
|
set_gdbarch_num_regs (gdbarch, CSKY_NUM_REGS);
|
|
|
|
|
set_gdbarch_pc_regnum (gdbarch, CSKY_PC_REGNUM);
|
|
|
|
|
set_gdbarch_sp_regnum (gdbarch, CSKY_SP_REGNUM);
|
|
|
|
|
set_gdbarch_register_name (gdbarch, csky_register_name);
|
|
|
|
|
set_gdbarch_register_type (gdbarch, csky_register_type);
|
|
|
|
|
set_gdbarch_read_pc (gdbarch, csky_read_pc);
|
|
|
|
|
set_gdbarch_write_pc (gdbarch, csky_write_pc);
|
|
|
|
|
csky_add_reggroups (gdbarch);
|
|
|
|
|
set_gdbarch_register_reggroup_p (gdbarch, csky_register_reggroup_p);
|
|
|
|
|
set_gdbarch_stab_reg_to_regnum (gdbarch, csky_dwarf_reg_to_regnum);
|
|
|
|
|
set_gdbarch_dwarf2_reg_to_regnum (gdbarch, csky_dwarf_reg_to_regnum);
|
|
|
|
|
dwarf2_frame_set_init_reg (gdbarch, csky_dwarf2_frame_init_reg);
|
|
|
|
|
|
|
|
|
|
/* Functions to analyze frames. */
|
|
|
|
|
frame_base_set_default (gdbarch, &csky_frame_base);
|
|
|
|
|
set_gdbarch_skip_prologue (gdbarch, csky_skip_prologue);
|
|
|
|
|
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
|
|
|
|
|
set_gdbarch_frame_align (gdbarch, csky_frame_align);
|
|
|
|
|
set_gdbarch_stack_frame_destroyed_p (gdbarch, csky_stack_frame_destroyed_p);
|
|
|
|
|
|
|
|
|
|
/* Functions handling dummy frames. */
|
|
|
|
|
set_gdbarch_push_dummy_call (gdbarch, csky_push_dummy_call);
|
|
|
|
|
|
|
|
|
|
/* Frame unwinders. Use DWARF debug info if available,
|
|
|
|
|
otherwise use our own unwinder. */
|
|
|
|
|
dwarf2_append_unwinders (gdbarch);
|
|
|
|
|
frame_unwind_append_unwinder (gdbarch, &csky_stub_unwind);
|
|
|
|
|
frame_unwind_append_unwinder (gdbarch, &csky_unwind_cache);
|
|
|
|
|
|
|
|
|
|
/* Hook in ABI-specific overrides, if they have been registered. */
|
|
|
|
|
gdbarch_init_osabi (info, gdbarch);
|
|
|
|
|
|
|
|
|
|
/* Support simple overlay manager. */
|
|
|
|
|
set_gdbarch_overlay_update (gdbarch, simple_overlay_update);
|
|
|
|
|
set_gdbarch_char_signed (gdbarch, 0);
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
|
|
|
|
|
if (tdesc_data != nullptr)
|
|
|
|
|
{
|
|
|
|
|
set_gdbarch_num_regs (gdbarch, (num_regs + 1));
|
|
|
|
|
tdesc_use_registers (gdbarch, info.target_desc, std::move (tdesc_data));
|
|
|
|
|
set_gdbarch_register_type (gdbarch, csky_register_type);
|
2022-07-22 10:33:14 +08:00
|
|
|
set_gdbarch_register_reggroup_p (gdbarch,
|
2023-03-09 14:56:09 -05:00
|
|
|
csky_register_reggroup_p);
|
gdb:csky add support target-descriptions for CSKY arch
Registers in CSKY architecture included:
1. 32 gprs
2. 16 ars (alternative gprs used for quick interrupt)
3. hi, lo, pc
4. fr0~fr31, fcsr, fid, fesr
5. vr0~vr15
6. ((32 banks) * 32) cr regs (max 32 banks, 32 control regs a bank)
For register names:
Except over control registers, other registers, like gprs, hi, lo ...
are fixed names. Among the 32*32 control registers, some used registers
will have fixed names, others will have a default name "cpxcry". 'x'
refers to bank, y refers index in the bank(a control register in bank
4 with index 14 will has a default name cp4cr14).
For register numbers in GDB:
We assign a fixed number to each register in GDB, like:
r0~r31 with 0~31
hi, lo with 36, 37
fpu/vpu with 40~71
...
described in function csky_get_supported_register_by_index().
Function csky_get_supported_tdesc_registers_count():
To calculate the total number of registers that GDB can analyze,
including those with fixed names and those with default register names.
Function csky_get_supported_register_by_index():
To find a supported struct csky_supported_tdesc_register, return a
struct include name with regnum via index.
Arrays csky_supported_tdesc_feature_names[]:
Include all supported feature names in tdesc-xmls.
We use the information described above to load the register description
file of the target from the stub. When loading, do a little check that
whether the register description file contains SP, LR and PC.
2022-06-13 19:17:58 +08:00
|
|
|
}
|
|
|
|
|
|
gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
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if (tdep->fv_pseudo_registers_count)
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{
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set_gdbarch_num_pseudo_regs (gdbarch,
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2023-03-09 14:56:09 -05:00
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tdep->fv_pseudo_registers_count);
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gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
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set_gdbarch_pseudo_register_read (gdbarch,
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2023-03-09 14:56:09 -05:00
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csky_pseudo_register_read);
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gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
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set_gdbarch_pseudo_register_write (gdbarch,
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2023-03-09 14:56:09 -05:00
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csky_pseudo_register_write);
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gdb:csky add pseudo regs for float and vector regs
In the existing CSKY architecture, there are at most 32 floating
and 16 vector registers. Float registers's count can be configured
as 16 or 32. In the future, the vector registers's count may be
extended to 32.
The bit width of floating-point register is 64bits, and the bit
width of vector register is 128bit.
Special points: in fr0~fr15 and vr0~vr15, each FRx is the lower
64 bits of the corresponding VRx.
Here, we will split each floating-point and vector register to
32bits wide, add the corresponding pseudo registers, and finally
use them for the dwarf registers.
There are 128 pseudo registers in total, s0~s127, including:
1. s0 and s1 correspond to fr0, s4 and s5 correspond to fr1, and so on.
Every two separated pseudo registers correspond to a float register.
2. s0, s1, s2 and s3 correspond to vr0; s4, s5, s6 and s7 correspond to vr1,
and so on. Every four pseudo registers corresponds to a vector register.
Therefore, in s64~s127, there are general registers that are not actually
used. This part is to prepare for the expansion of vector registers to 32
Therefore, in s64~s127, half of the registers are actually unused. This
part is to prepare for the expansion of the vector register to 32.
2022-06-28 11:05:30 +08:00
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set_tdesc_pseudo_register_name (gdbarch, csky_pseudo_register_name);
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}
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2018-07-25 10:43:22 +01:00
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return gdbarch;
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}
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2020-01-13 14:01:38 -05:00
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void _initialize_csky_tdep ();
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2018-07-25 10:43:22 +01:00
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void
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2020-01-13 14:01:38 -05:00
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_initialize_csky_tdep ()
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2018-07-25 10:43:22 +01:00
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{
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2022-07-31 10:44:01 -06:00
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gdbarch_register (bfd_arch_csky, csky_gdbarch_init);
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2018-07-25 10:43:22 +01:00
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csky_init_reggroup ();
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/* Allow debugging this file's internals. */
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add_setshow_boolean_cmd ("csky", class_maintenance, &csky_debug,
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_("Set C-Sky debugging."),
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_("Show C-Sky debugging."),
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_("When on, C-Sky specific debugging is enabled."),
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NULL,
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NULL,
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&setdebuglist, &showdebuglist);
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}
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