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x86: replace adhoc ambiguous operand checking for CRC32 There's no need (anymore?) to heavily special case this - just make generic logic consider only its first operand, and deal with the case of an 'l' suffix not being allowed in a pattern.
2020-01-21 08:30:05 +01:00
2020-01-21 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Merge CRC32 handling into
generic code path. Deal with No_lSuf being set in a template.
* testsuite/gas/i386/inval-crc32.l,
testsuite/gas/i386/x86-64-inval-crc32.l: Expect warning(s)
instead of error(s) when operand size is ambiguous.
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
testsuite/gas/i386/noreg64.s: Add CRC32 tests.
* testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.l,
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.l,
testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l:
Adjust expectations.
x86: improve handling of insns with ambiguous operand sizes Commit b76bc5d54e ("x86: don't default variable shift count insns to 8-bit operand size") pointed out a very bad case, but the underlying problem is, as mentioned on various occasions, much larger: Silently selecting a (nowhere documented afaict) certain default operand size when there's no "sizing" suffix and no suitable register operand(s) is simply dangerous (for the programmer to make mistakes). While in Intel syntax mode such mistakes already lead to an error (which is going to remain that way), AT&T syntax mode now gains warnings in such cases by default, which can be suppressed or promoted to an error if so desired by the programmer. Furthermore at least general purpose insns now consistently have a default applied (alongside the warning emission), rather than accepting some and refusing others. No warnings are (as before) to be generated for "DefaultSize" insns as well as ones acting on selector and other fixed-width values. For SYSRET, however, the DefaultSize needs to be dropped - it had been wrongly put there in the first place, as it's unrelated to .code16gcc (no stack accesses involved). As set forth as a prereq when I first mentioned this intended change a few years back, Linux as well as gcc have meanwhile been patched to avoid (emission of) ambiguous operands (and hence triggering of the new warning). Note that I think that in 64-bit mode IRET and far RET would better get a diagnostic too, as it's reasonably likely that a suffix-less instance really is meant to be a 64-bit one. But I guess I better make this a separate follow-on patch. Note further that floating point operations with integer operands are an exception for now: They continue to use short (16-bit) operands by default even in 32- and 64-bit modes. Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also need to be diagnosed, with their 64-bit forms not being very useful I think it is better to continue to avoid warning about them (by way of them carrying IgnoreSize attributes).
2020-01-21 08:28:25 +01:00
2020-01-21 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Drop SYSRET special case
and an intel_syntax check. Re-write lack-of-suffix processing
logic.
* doc/c-i386.texi: Document operand size defaults for suffix-
less AT&T syntax insns.
* testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
testsuite/gas/i386/x86-64-avx-scalar.s,
testsuite/gas/i386/x86-64-avx.s,
testsuite/gas/i386/x86-64-bundle.s,
testsuite/gas/i386/x86-64-intel64.s,
testsuite/gas/i386/x86-64-lock-1.s,
testsuite/gas/i386/x86-64-opcode.s,
testsuite/gas/i386/x86-64-sse2avx.s,
testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
* testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
testsuite/gas/i386/x86-64-nops.s,
testsuite/gas/i386/x86-64-ptwrite.s,
testsuite/gas/i386/x86-64-simd.s,
testsuite/gas/i386/x86-64-sse-noavx.s,
testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less
insns.
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
testsuite/gas/i386/noreg64.s: Add further tests.
* testsuite/gas/i386/ilp32/x86-64-nops.d,
testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
testsuite/gas/i386/sse-noavx.d,
testsuite/gas/i386/x86-64-intel64.d,
testsuite/gas/i386/x86-64-nops.d,
testsuite/gas/i386/x86-64-opcode.d,
testsuite/gas/i386/x86-64-ptwrite-intel.d,
testsuite/gas/i386/x86-64-ptwrite.d,
testsuite/gas/i386/x86-64-simd-intel.d,
testsuite/gas/i386/x86-64-simd-suffix.d,
testsuite/gas/i386/x86-64-simd.d,
testsuite/gas/i386/x86-64-sse-noavx.d
testsuite/gas/i386/x86-64-suffix.d,
testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations.
* testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
testsuite/gas/i386/noreg64.l: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86: VCVTNEPS2BF16{X,Y} should permit broadcasting Just like other VCVT*{X,Y} templates do, and to allow the programmer flexibility (might be relevant in particular when heavily macro-izing code), the two templates should also have Broadcast set, just like their X/Y-suffix-less counterparts. This in turn requires them to also have * Dword set on their memory operands, to cover the logic added to i386gen by 4a1b91eabbe7 ("x86: Expand Broadcast to 3 bits"), * RegXMM/RegYMM set on their source operands, to satisfy broadcast sizing logic in gas itself. Otherwise ATTSyntax templates wouldn't need such operand size attributes. While extending the test cases, also add Intel syntax broadcast forms without explicit size specifiers.
2020-01-21 08:25:31 +01:00
2020-01-21 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512_bf16_vl.s,
testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Add broadcast forms
of VCVTNEPS2BF16{X,Y}. Add operand-size less Intel syntax
broadcast forms of VCVTNEPS2BF16.
* testsuite/gas/i386/avx512_bf16_vl.d,
testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Adjust expectations.
Updated translations for various binutils sub-directories
2020-01-20 15:10:23 +00:00
2020-01-20 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
x86-64: Fix TLSDESC relaxation for x32 For x32, we must encode "lea x@TLSDESC(%rip), %reg" with a REX prefix even if it isn't required. Otherwise linker can’t safely perform GDesc -> IE/LE optimization. X32 TLSDESC sequences can be: 40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg ... 67 ff 10 call *x@TLSCALL(%eax) or the same sequence as LP64: 48 8d 05 00 00 00 00 lea foo@TLSDESC(%rip), %reg ... ff 10 call *foo@TLSCALL(%rax) We need to support both sequences for x32. For both GDesc -> IE/LE transitions, 67 ff 10 call *x@TLSCALL(%eax) should relaxed to 0f 1f 00 nopl (%rax) For GDesc -> LE transition, 40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg should relaxed to 40 c7 c0 fc ff ff ff rex movl $x@tpoff, %reg For GDesc -> IE transition, 40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg should relaxed to 40 8b 05 00 00 00 00 rex movl x@gottpoff(%rip), %eax bfd/ PR ld/25416 * elf64-x86-64.c (elf_x86_64_check_tls_transition): Support "rex leal x@tlsdesc(%rip), %reg" and "call *x@tlsdesc(%eax)" in X32 mode. (elf_x86_64_relocate_section): In x32 mode, for GDesc -> LE transition, relax "rex leal x@tlsdesc(%rip), %reg" to "rex movl $x@tpoff, %reg", for GDesc -> IE transition, relax "rex leal x@tlsdesc(%rip), %reg" to "rex movl x@gottpoff(%rip), %eax". For both transitions, relax "call *(%eax)" to "nopl (%rax)". gas/ PR ld/25416 * config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix for lea with R_X86_64_GOTPC32_TLSDESC relocation when generating x32 object. * testsuite/gas/i386/ilp32/x32-tls.d: Updated. * testsuite/gas/i386/ilp32/x32-tls.s: Add tests for lea with R_X86_64_GOTPC32_TLSDESC relocation. ld/ PR ld/25416 * testsuite/ld-x86-64/pr25416-1.s: New file * testsuite/ld-x86-64/pr25416-1a.d: Likewise. * testsuite/ld-x86-64/pr25416-1b.d: Likewise. * testsuite/ld-x86-64/pr25416-1.s: Likewise. * testsuite/ld-x86-64/pr25416-2.s: Likewise. * testsuite/ld-x86-64/pr25416-2a.d: Likewise. * testsuite/ld-x86-64/pr25416-2b.d: Likewise. * testsuite/ld-x86-64/pr25416-3.d: Likewise. * testsuite/ld-x86-64/pr25416-3.s: Likewise. * testsuite/ld-x86-64/pr25416-4.d: Likewise. * testsuite/ld-x86-64/pr25416-4.s: Likewise. * testsuite/ld-x86-64/pr25416-5a.c: Likewise. * testsuite/ld-x86-64/pr25416-5b.s: Likewise. * testsuite/ld-x86-64/pr25416-5c.s: Likewise. * testsuite/ld-x86-64/pr25416-5d.s: Likewise. * testsuite/ld-x86-64/pr25416-5e.s: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run PR ld/25416 tests.
2020-01-20 06:58:51 -08:00
2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
PR ld/25416
* config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
for lea with R_X86_64_GOTPC32_TLSDESC relocation when generating
x32 object.
* testsuite/gas/i386/ilp32/x32-tls.d: Updated.
* testsuite/gas/i386/ilp32/x32-tls.s: Add tests for lea with
R_X86_64_GOTPC32_TLSDESC relocation.
Update version to 2.34.50. Regenerate configure and .pot files.
2020-01-18 14:12:07 +00:00
2020-01-18 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/gas.pot: Regenerate.
Add markers for 2.34 branch to the NEWS files and ChangeLogs.
2020-01-18 13:50:25 +00:00
2020-01-18 Nick Clifton <nickc@redhat.com>
Binutils 2.34 branch created.
x86: Add {vex} pseudo prefix There are 2-byte VEX prefix and 3-byte VEX prefix. 2-byte VEX prefix can't encode all operands. By default, assembler tries 2-byte VEX prefix first. {vex3} can be used to force 3-byte VEX prefix. This patch adds {vex} pseudo prefix and keeps {vex2} for backward compatibility. gas/ * config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2 with vex_encoding_vex. (parse_insn): Likewise. * doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex} and {vex3} documentation. * testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with {vex}. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. opcodes/ * i386-opc.tbl: Add {vex} pseudo prefix. * i386-tbl.h: Regenerated.
2020-01-17 07:07:55 -08:00
2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
with vex_encoding_vex.
(parse_insn): Likewise.
* doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex}
and {vex3} documentation.
* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
{vex}.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
[binutils][arm] PR25376 Change MVE into a CORE_HIGH feature This patch moves MVE feature bits into the CORE_HIGH section. This makes sure .fpu and -mfpu does not reset the bits set by MVE. This is important because .fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose to define MVE as an architecture extension rather than put it together with other the legacy fpu features. This will enable the following behavior: .arch armv8.1-m.main .arch mve .fpu fpv5-sp-d16 #does not disable mve. vadd.i32 q0, q1, q2 This patch also makes sure MVE is not taken into account during auto-detect. This was already the case, but because we moved the MVE bits to the architecture feature space we must make sure ARM_ANY does not include MVE. gas/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH. (armv8_1m_main_ext_table): Use CORE_HIGH for mve. * testsuite/arm/armv8_1-m-fpu-mve-1.s: New. * testsuite/arm/armv8_1-m-fpu-mve-1.d: New. * testsuite/arm/armv8_1-m-fpu-mve-2.s: New. * testsuite/arm/armv8_1-m-fpu-mve-2.d: New. include/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to... (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space. (ARM_ANY): Redefine to not include any MVE bits. (ARM_FEATURE_ALL): Removed. opcodes/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. (neon_opcodes): Likewise. (select_arm_features): Make sure we enable MVE bits when selecting armv8.1-m.main. Make sure we do not enable MVE bits when not selecting any architecture.
2020-01-16 13:50:52 +00:00
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.
x86: drop found_cpu_match local variable 50aecf8c5f could have done so right away; perhaps the variable shouldn't have been introduced in the first place.
2020-01-16 10:07:36 +01:00
2020-01-16 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_template): Drop found_cpu_match local
variable.
x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit mode The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand forms accepted even outside of 64-bit mode, and this even without any {evex} pseudo-prefix (otherwise one could argue that this is an attempt to follow one possible, albeit somewhat odd, interpretation of the SDM wording to this effect). For consistency between the various involved templates drop the * (now) unnecessary IgnoreSize attributes * unnecessary (due to VexW1) Size64 attributes from VEX encoded forms * redundant (with Reg64) Qword operand attributes uniformly.
2020-01-16 10:05:35 +01:00
2020-01-16 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512dq-inval.l,
testsuite/gas/i386/avx512dq-inval.s: New.
* testsuite/gas/i386/i386.exp: Run new test.
MSP430: Fix relocation overflow when using #lo(EXP) macro gas/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X relocations when the target is 430X, except when extracting part of an expression. (msp430_srcoperand): Adjust comment. Initialize the expp member of the msp430_operand_s struct as appropriate. (msp430_dstoperand): Likewise. * testsuite/gas/msp430/msp430.exp: Run new test. * testsuite/gas/msp430/reloc-lo-430x.d: New test. * testsuite/gas/msp430/reloc-lo-430x.s: New test. include/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * opcode/msp430.h (enum msp430_expp_e): New. (struct msp430_operand_s): Add expp member to struct. ld/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * testsuite/ld-msp430-elf/msp430-elf.exp: Run new test. * testsuite/ld-msp430-elf/reloc-lo-430x.s: New test.
2020-01-15 13:17:27 +00:00
2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X
relocations when the target is 430X, except when extracting part of an
expression.
(msp430_srcoperand): Adjust comment.
Initialize the expp member of the msp430_operand_s struct as
appropriate.
(msp430_dstoperand): Likewise.
* testsuite/gas/msp430/msp430.exp: Run new test.
* testsuite/gas/msp430/reloc-lo-430x.d: New test.
* testsuite/gas/msp430/reloc-lo-430x.s: New test.
Reinstate gas em=freebsd for sparc-freebsd In commit c9098af41e3 I over-simplified the sparc target decoding, missing the fact that prior to that patch sparc-*-freebsd fell through to the generic *-*-freebsd match. * configure.tgt: Add sparc-*-freebsd case.
2020-01-15 16:15:43 +10:30
2020-01-15 Alan Modra <amodra@gmail.com>
* configure.tgt: Add sparc-*-freebsd case.
x86: Updated align branch tests for Darwin and i686-pc-elf 1. Update align branch assembler tests to match Darwin disassembler outputs. 2. Skip unsupported "call *foo" tests in 64-bit mode on Darwin. 3. Update align branch linker test to match any addresses for i686-pc-elf. gas/ * testsuite/gas/i386/align-branch-1a.d: Updated for Darwin. * testsuite/gas/i386/align-branch-1b.d: Likewise. * testsuite/gas/i386/align-branch-1c.d: Likewise. * testsuite/gas/i386/align-branch-1d.d: Likewise. * testsuite/gas/i386/align-branch-1e.d: Likewise. * testsuite/gas/i386/align-branch-1f.d: Likewise. * testsuite/gas/i386/align-branch-1g.d: Likewise. * testsuite/gas/i386/align-branch-1h.d: Likewise. * testsuite/gas/i386/align-branch-1i.d: Likewise. * testsuite/gas/i386/align-branch-5.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1i.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-5.d: Likewise. * testsuite/gas/i386/i386.exp: Skip x86-64-align-branch-2a, x86-64-align-branch-2b and x86-64-align-branch-2c on Darwin. ld/ * testsuite/ld-i386/align-branch-1.d: Updated for i686-pc-elf.
2020-01-14 08:59:37 -08:00
2020-01-14 Lili Cui <lili.cui@intel.com>
* testsuite/gas/i386/align-branch-1a.d: Updated for Darwin.
* testsuite/gas/i386/align-branch-1b.d: Likewise.
* testsuite/gas/i386/align-branch-1c.d: Likewise.
* testsuite/gas/i386/align-branch-1d.d: Likewise.
* testsuite/gas/i386/align-branch-1e.d: Likewise.
* testsuite/gas/i386/align-branch-1f.d: Likewise.
* testsuite/gas/i386/align-branch-1g.d: Likewise.
* testsuite/gas/i386/align-branch-1h.d: Likewise.
* testsuite/gas/i386/align-branch-1i.d: Likewise.
* testsuite/gas/i386/align-branch-5.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1i.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-5.d: Likewise.
* testsuite/gas/i386/i386.exp: Skip x86-64-align-branch-2a,
x86-64-align-branch-2b and x86-64-align-branch-2c on Darwin.
Fix various assembler testsuite failures for the Z80 target. PR 25377 gas * config/tc-z80.c: Add support for half precision, single precision and double precision floating point values. * config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes. * doc/as.texi: Add new z80 command line options. * doc/c-z80.texi: Document new z80 command line options. * testsuite/gas/z80/ez80_pref_dis.s: New test. * testsuite/gas/z80/ez80_pref_dis.d: New test driver. * testsuite/gas/z80/z80.exp: Run the new test. * testsuite/gas/z80/fp_math48.d: Use correct command line option. * testsuite/gas/z80/fp_zeda32.d: Likewise. * testsuite/gas/z80/strings.d: Update expected output. opcodes * z80-dis.c (suffix): Use .db instruction to generate double prefix.
2020-01-14 13:13:57 +00:00
2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25377
* config/tc-z80.c: Add support for half precision, single
precision and double precision floating point values.
* config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes.
* doc/as.texi: Add new z80 command line options.
* doc/c-z80.texi: Document new z80 command line options.
* testsuite/gas/z80/ez80_pref_dis.s: New test.
* testsuite/gas/z80/ez80_pref_dis.d: New test driver.
* testsuite/gas/z80/z80.exp: Run the new test.
* testsuite/gas/z80/fp_math48.d: Use correct command line option.
* testsuite/gas/z80/fp_zeda32.d: Likewise.
* testsuite/gas/z80/strings.d: Update expected output.
[gas][aarch64] Turn on SVE when using f32mm or f64mm extensions There are no instructions under these matrix multiply extensions that can be used without having SVE enabled. Since these extensions require SVE, we make that explicit in the options table. Tested on aarch64-none-elf without regressions. gas/ChangeLog: 2020-01-13 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (f64mm, f32mm): Add sve as a feature dependency.
2020-01-13 15:31:39 +00:00
2020-01-13 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (f64mm, f32mm): Add sve as a feature
dependency.
[ARC][committed] Code cleanup and improvements. Code clean up and improvements when changing the cpu from command line. Also, remove unused/old emulations. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change the CPU. * config/tc-arc.h: Add header if/defs. * testsuite/gas/arc/pseudos.d: Improve matching pattern. ls/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * Makefile.am: Remove earcelf_prof.c and earclinux_prof.c emulations. * Makefile.in: Regenerate. * configure.tgt: Likewise. * emulparams/arcelf_prof.sh: Remove file. * emulparams/arclinux_prof.sh: Likewise. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (C_NE): Make it required.
2020-01-13 11:16:47 +02:00
2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
* config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change
the CPU.
* config/tc-arc.h: Add header if/defs.
* testsuite/gas/arc/pseudos.d: Improve matching pattern.
ubsan: wasm32: signed integer overflow The signed integer overflow occurred when adding one to target_count for (i = 0; i < target_count + 1; i++) but that's the least of the worries here. target_count was long and i int, leading to the possibility of a loop that never ended. So to avoid this type of vulnerability, this patch uses what I believe to be the proper types for arguments of various wasm32 opcodes, rather than using "long" which may change in size. gas/ * testsuite/gas/wasm32/allinsn.d: Update expected output. opcodes/ * wasm32-dis.c (print_insn_wasm32): Localise variables. Store result of wasm_read_leb128 in a uint64_t and check that bits are not lost when copying to other locals. Use uint32_t for most locals. Use PRId64 when printing int64_t.
2020-01-13 14:27:19 +10:30
2020-01-13 Alan Modra <amodra@gmail.com>
* testsuite/gas/wasm32/allinsn.d: Update expected output.
tic4x: sign extension using shifts Don't do that. Especially don't use shift counts that assume the type being shifted is 32 bits when the type is long/unsigned long. Also reverts part of a change I made on 2019-12-11 to tic4x_print_register that on closer inspection turns out to be unnecessary. include/ * opcode/tic4x.h (EXTR): Delete. (EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign extension using shifts. Do trim INSERTU value to specified bitfield. opcodes/ * tic4x-dis.c (tic4x_print_register): Remove dead code. gas/ * config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap insertion.
2020-01-12 20:16:22 +10:30
2020-01-13 Alan Modra <amodra@gmail.com>
* config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap
insertion.
HPUX gas testsuite fixes * testsuite/gas/elf/pr14891.s: Don't start directives in first column. * testsuite/gas/elf/pr21661.d: Don't run on hpux.
2020-01-10 17:29:59 +10:30
2020-01-10 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/pr14891.s: Don't start directives in first column.
* testsuite/gas/elf/pr21661.d: Don't run on hpux.
Fix compile time warnings about comparisons always being false. PR 25224 gas * config/tc-z80.c (emit_ld_m_rr): Use integer types when checking opcode byte values. (emit_ld_r_r): Likewise. (emit_ld_rr_m): Likewise. (emit_ld_rr_nn): Likewise. opcodes * z80-dis.c (ld_ii_ii): Use character constant when checking opcode byte value.
2020-01-09 11:47:44 +00:00
2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25224
* config/tc-z80.c (emit_ld_m_rr): Use integer types when checking
opcode byte values.
(emit_ld_r_r): Likewise.
(emit_ld_rr_m): Likewise.
(emit_ld_rr_nn): Likewise.
x86: refine when to trigger optimizations Checking just the base opcode without also checking this isn't a VEX encoding, and without there being other insn properties avoiding a match once respective VEX/XOP/EXEX-encoded insns would appear, is at least dangerous. Add respective checks. At the same time there's no real need to check the extension opcode to be None for the 0xA8 form - there's nothing it can be confused with, and non-VEX-and-alike forms also can't appear.
2020-01-09 11:40:04 +01:00
2020-01-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding): Add
is_any_vex_encoding() invocations. Drop respective
i.tm.extension_opcode == None checks.
x86-64: assert sane internal state for REX conversions For the comments about "hi" registers to be really applicable, RegRex may not be set on the respective registers. Assert this is the case.
2020-01-09 11:39:33 +01:00
2020-01-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Check RegRex is clear during
REX transformations. Correct comment indentation.
x86: consistently convert to byte registers for TEST w/ imm optimization Commit ac0ab1842d ("i386: Also check R12-R15 registers when optimizing testq to testb") didn't go quite far enough: In order to avoid confusing other code registers would better be converted to byte ones uniformly.
2020-01-09 11:38:59 +01:00
2020-01-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding): Generalize register
transformation for TEST optimization.
x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMD The disassembler change is such that in default mode we'd disassemble the insns (for there not ebing any conflicts), but when AMD64 mode was explicitly requested, we'd show them as "(bad)".
2020-01-09 11:38:01 +01:00
2020-01-09 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-sysenter-amd.s,
testsuite/gas/i386/x86-64-sysenter-amd.d,
testsuite/gas/i386/x86-64-sysenter-amd.l,
testsuite/gas/i386/x86-64-sysenter-intel.d,
testsuite/gas/i386/x86-64-sysenter-mixed.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
Document the fact that the assembler's alignment pseudo-ops can be issued without any argumemtns. PR 25284 * doc/as.texi (Align): Document the fact that all arguments can be omitted. (Balign): Likewise. (P2align): Likewise.
2020-01-08 17:00:54 +00:00
2020-01-08 Nick Clifton <nickc@redhat.com>
PR 25284
* doc/as.texi (Align): Document the fact that all arguments can be
omitted.
(Balign): Likewise.
(P2align): Likewise.
Make the assembler generate an error if there is an attempt to define a section with the same name as an already defined symbol. PR 14891 * config/obj-elf.c (obj_elf_section): Fail if the section name is already defined as a different symbol type. * testsuite/gas/elf/pr14891.s: New test source file. * testsuite/gas/elf/pr14891.d: New test driver. * testsuite/gas/elf/pr14891.s: New test expected error output. * testsuite/gas/elf/elf.exp: Run the new test.
2020-01-08 16:30:20 +00:00
2020-01-08 Nick Clifton <nickc@redhat.com>
PR 14891
* config/obj-elf.c (obj_elf_section): Fail if the section name is
already defined as a different symbol type.
* testsuite/gas/elf/pr14891.s: New test source file.
* testsuite/gas/elf/pr14891.d: New test driver.
* testsuite/gas/elf/pr14891.s: New test expected error output.
* testsuite/gas/elf/elf.exp: Run the new test.
ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]' The fix is the additional ARRAY_SIZE test, the rest just tidies variable types rather than adding a cast to avoid warnings. opcodes/ * z8k-dis.c: Include libiberty.h (instr_data_s): Make max_fetched unsigned. (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. Don't exceed byte_info bounds. (output_instr): Make num_bytes unsigned. (unpack_instr): Likewise for nibl_count and loop. * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and idx unsigned. * z8k-opc.h: Regenerate. gas/ * config/tc-z8k.c (md_begin): Make idx unsigned. (get_specific): Likewise for this_index.
2020-01-08 11:42:36 +10:30
2020-01-08 Alan Modra <amodra@gmail.com>
* config/tc-z8k.c (md_begin): Make idx unsigned.
(get_specific): Likewise for this_index.
[ARC] Improve parsing instruction operands. We use gas' expression function to parse the operands of an instruction in a generic way. There are situations when we have labels and registers having the same name as well as the substraction sign doesn't always stands for the arithmetical operation but for the register range (e.g. enter instruction). This patch improves parsing symbols found in a instruction operand, cleans up code and avoids using default or undefined variables. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (parse_reloc_symbol): New function. (tokenize_arguments): Clean up, use parse_reloc_symbol function. (md_operand): Set X_md to absent. (arc_parse_name): Check for X_md.
2020-01-07 15:29:16 +02:00
2020-01-07 Claudiu Zissulescu <claziss@synopsys.com>
* onfig/tc-arc.c (parse_reloc_symbol): New function.
(tokenize_arguments): Clean up, use parse_reloc_symbol function.
(md_operand): Set X_md to absent.
(arc_parse_name): Check for X_md.
Allow individual targets to decide if string escapes should be allowed. Disable for PPC and Z80. PR 25311 * as.h (TC_STRING_ESCAPES): Provide a default definition. * app.c (do_scrub_chars): Use TC_STRING_ESCAPES instead of NO_STRING_ESCAPES. * read.c (next_char_of_string): Likewise. * config/tc-ppc.h (TC_STRING_ESCAPES): Define. * config/tc-z80.h (TC_STRING_ESCAPES): Define.
2020-01-03 16:23:19 +00:00
2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25311
* as.h (TC_STRING_ESCAPES): Provide a default definition.
* app.c (do_scrub_chars): Use TC_STRING_ESCAPES instead of
NO_STRING_ESCAPES.
* read.c (next_char_of_string): Likewise.
* config/tc-ppc.h (TC_STRING_ESCAPES): Define.
* config/tc-z80.h (TC_STRING_ESCAPES): Define.
Updated Swedish translation for the GAS subdirectory.
2020-01-03 12:59:54 +00:00
2020-01-03 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
Arm64: correct address index operands for LD1RO{H,W,D} Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03 10:16:44 +01:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/f64mm.s: Scale index of LD1RO{H,W,D}.
* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
Arm64: correct {su,us}dot SIMD encodings According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
2020-01-03 10:14:16 +01:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/i8mm.s: Add 128-bit form tests for
by-element usdot. Add 64-bit form tests for by-element sudot.
* testsuite/gas/aarch64/i8mm.d: Adjust expectations.
Arm64: correct uzp{1,2} mnemonics According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
2020-01-03 10:13:31 +01:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/f64mm.s: Drop 'i' from uzip<n>.
* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
Arm64: correct 64-bit element fmmla encoding There's just one bit of difference to the 32-bit element form, as per the documentation.
2020-01-03 10:12:49 +01:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/f64mm.d,
testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations.
Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02 14:10:40 +00:00
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
* config/tc-z80.c: Add new architectures: Z180 and eZ80. Add
support for assembler code generated by SDCC. Add new relocation
types. Add z80-elf target support.
* config/tc-z80.h: Add z80-elf target support. Enable dollar local
labels. Local labels starts from ".L".
* NEWS: Mention the new support.
* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
* testsuite/gas/all/fwdexp.s: Likewise.
* testsuite/gas/all/cond.l: Likewise.
* testsuite/gas/all/cond.s: Likewise.
* testsuite/gas/all/fwdexp.d: Likewise.
* testsuite/gas/all/fwdexp.s: Likewise.
* testsuite/gas/elf/section2.e-mips: Likewise.
* testsuite/gas/elf/section2.l: Likewise.
* testsuite/gas/elf/section2.s: Likewise.
* testsuite/gas/macros/app1.d: Likewise.
* testsuite/gas/macros/app1.s: Likewise.
* testsuite/gas/macros/app2.d: Likewise.
* testsuite/gas/macros/app2.s: Likewise.
* testsuite/gas/macros/app3.d: Likewise.
* testsuite/gas/macros/app3.s: Likewise.
* testsuite/gas/macros/app4.d: Likewise.
* testsuite/gas/macros/app4.s: Likewise.
* testsuite/gas/macros/app4b.s: Likewise.
* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
* testsuite/gas/z80/z80.exp: Add new tests
* testsuite/gas/z80/dollar.d: New file.
* testsuite/gas/z80/dollar.s: New file.
* testsuite/gas/z80/ez80_adl_all.d: New file.
* testsuite/gas/z80/ez80_adl_all.s: New file.
* testsuite/gas/z80/ez80_adl_suf.d: New file.
* testsuite/gas/z80/ez80_isuf.s: New file.
* testsuite/gas/z80/ez80_z80_all.d: New file.
* testsuite/gas/z80/ez80_z80_all.s: New file.
* testsuite/gas/z80/ez80_z80_suf.d: New file.
* testsuite/gas/z80/r800_extra.d: New file.
* testsuite/gas/z80/r800_extra.s: New file.
* testsuite/gas/z80/r800_ii8.d: New file.
* testsuite/gas/z80/r800_z80_doc.d: New file.
* testsuite/gas/z80/z180.d: New file.
* testsuite/gas/z80/z180.s: New file.
* testsuite/gas/z80/z180_z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.s: New file.
* testsuite/gas/z80/z80_ii8.d: New file.
* testsuite/gas/z80/z80_ii8.s: New file.
* testsuite/gas/z80/z80_in_f_c.d: New file.
* testsuite/gas/z80/z80_in_f_c.s: New file.
* testsuite/gas/z80/z80_op_ii_ld.d: New file.
* testsuite/gas/z80/z80_op_ii_ld.s: New file.
* testsuite/gas/z80/z80_out_c_0.d: New file.
* testsuite/gas/z80/z80_out_c_0.s: New file.
* testsuite/gas/z80/z80_reloc.d: New file.
* testsuite/gas/z80/z80_reloc.s: New file.
* testsuite/gas/z80/z80_sli.d: New file.
* testsuite/gas/z80/z80_sli.s: New file.
[ARM][gas] fix build breakage with gcc-10 by using correct enum type Fixes ../../gas/config/tc-arm.c: In function 'parse_reg_list': ../../gas/config/tc-arm.c:1946:35: error: implicit conversion from 'enum reg_list_els' to 'enum arm_reg_type' [-Werror=enum-conversion] 1946 | reg = arm_reg_parse (&str, REGLIST_RN); | ^~~~~~~~~~ gas/ChangeLog: * config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of REGLIST_RN.
2019-10-21 16:59:11 +01:00
2020-01-02 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of
REGLIST_RN.
Re: Update year range in copyright notice of binutils files Add the ChangeLog entry.
2020-01-01 18:52:19 +10:30
2020-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2020-01-01 18:07:11 +10:30
For older changes see ChangeLog-2019
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 21:14:31 +10:30
ChangeLog rotation
2020-01-01 18:07:11 +10:30
Copyright (C) 2020 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 21:14:31 +10:30
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
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Local Variables:
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left-margin: 8
fill-column: 74
version-control: never
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